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| Revisiting graph coloring register allocation : a study of the Chaitin-Briggs and Callahan-Koblenz algorithms | |
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| Register pressure in software-pipelined loop nests : fast computation and impact on architecture design | |
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| Manipulating MAXLIVE for spill-free register allocation | |
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| Optimizing packet accesses for a domain specific language on network processors | |
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| Array replication to increase parallelism in applications mapped to configurable architectures | |
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| Generation of control and data flow graphs from scheduled and pipelined assembly code | |
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| Applying data copy to improve memory performance of general array computations | |
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| A cache-conscious profitability model for empirical tuning of loop fusion | |
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| Optimizing matrix multiplication with a classifier learning system | |
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| A language for the compact representation of multiple program versions | |
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| Efficient computation of may-happen-in-parallel information for concurrent Java programs | |
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| Evaluating the impact of thread escape analysis on a memory consistency model-aware compiler | |
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| Concurrency analysis for parallel programs with textually aligned barriers | |
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| Titanium performance and potential : an NPB experimental study | |
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| Efficient search-space pruning for integrated fusion and tiling transformations | |
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| Automatic measurement of instruction cache capacity | |
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| Combined ILP and register tiling : analytical model and optimization framework | |
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| Analytic models and empirical search : a hybrid approach to code optimization | |
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| Testing speculative work in a lazy/eager parallel functional language | |
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| Loop selection for thread-level speculation | |
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| Software thread level speculation for the Java language and virtual machine environment | |
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| Lightweight monitoring of the progress of remotely executing computations | |
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| Using platform-specific performance counters for dynamic compilation | |
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| A domain-specific interpreter for parallelizing a large mixed-language visualisation application | |
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| Compiler control power saving scheme for multi core processors | |
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| Code transformations for one-pass analysis | |
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| Scalable array SSA and array data flow analysis | |
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| Interprocedural symbolic range propagation for optimizing compilers | |
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| Parallelization of utility programs based on behavior phase analysis | |
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| A systematic approach to model-guided empirical search for memory hierarchy optimization | |
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| An efficient approach for self-scheduling parallel loops on multiprogrammed parallel computers | |
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| Dynamic compilation for reducing energy consumption of I/O-intensive applications | |
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| Supporting SELL for high-performance computing | |
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| Compiler supports and optimizations for PAC VLIW DSP processors | |
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