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Student's Guide to VHDL

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ISBN-10: 1558608656

ISBN-13: 9781558608658

Edition: 2nd 2008 (Revised)

Authors: Peter J. Ashenden

List price: $43.95
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"The Student's Guide to VHDL" is a condensed edition of "The Designer's Guide to VHDL," the most widely used textbook on VHDL for digital system modeling. "The Student's Guide" is targeted as a supplemental reference book for computer organization and digital design courses. Since publication of the first edition of "The Student's Guide," the IEEE VHDL and related standards have been revised. The "Designer's Guide" has been revised to reflect the changes, so it is appropriate that "The Student's Guide" also be revised. "In The Student's Guide to VHDL, 2nd Edition," we have included a design case study illustrating an FPGA-based design flow. The aim is to show how VHDL modeling fits into a…    
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Book details

List price: $43.95
Edition: 2nd
Copyright year: 2008
Publisher: Elsevier Science & Technology Books
Publication date: 5/19/2008
Binding: Paperback
Pages: 528
Size: 7.75" wide x 9.00" long x 1.00" tall
Weight: 1.980
Language: English

Fundamental Concepts
Modeling Digital Systems
Domains and Levels of Modeling
Modeling Example
Modeling Languages
VHDL Modeling Concepts
Elements of Behavior
Elements of Structure
Mixed Structural and Behavioral Models
Test Benches
Analysis, Elaboration and Execution
Learning a New Language: Lexical Elements and Syntax
Lexical Elements
Reserved Words
Special Symbols
Bit Strings
Syntax Descriptions
Scalar Data Types and Operations
Constants and Variables
Constant and Variable Declarations
Variable Assignment
Scalar Types
Type Declarations
Integer Types
Floating-Point Types
Physical Types
Enumeration Types
Standard Logic
Condition Conversion
Type Classification
Type Qualification
Type Conversion
Attributes of Scalar Types
Expressions and Predefined Operations
Sequential Statements
If Statements
Case Statements
Null Statements
Loop Statements
Exit Statements
Next Statements
While Loops
For Loops
Summary of Loop Statements
Assertion and Report Statements
Composite Data Types and Operations
Multidimensional Arrays
Array Aggregates
Array Attributes
Unconstrained Array Types
Predefined Array Types
Boolean Vectors, Integer Vectors, Real Vectors, and Time Vectors
Bit Vectors
Standard-Logic Arrays
String and Bit-String Literals
Unconstrained Array Element Types
Unconstrained Array Ports
Array Operations and Referencing
Logical Operators
Shift Operators
Relational Operators
Maximum and Minimum Operations
The Concatenation Operator
To_String Operations
Array Slices
Array Type Conversions
Arrays in Case Statements
Matching Case Statements
Record Aggregates
Unconstrained Record Element Types
Basic Modeling Constructs
Entity Declarations and Architecture Bodies
Concurrent Statements
Signal Declarations
Behavioral Descriptions
Signal Assignment
Conditional Signal Assignments
Selected Signal Assignments
Signal Attributes
Wait Statements
Delta Delays
Transport and Inertial Delay Mechanisms
Process Statements
Concurrent Signal Assignment Statements
Concurrent Simple Signal Assignments
Concurrent Conditional Signal Assignment
Concurrent Selected Signal Assignments
Concurrent Assertion Statements
Entities and Passive Processes
Structural Descriptions
Design Processing
Design Libraries and Contexts
Return Statement in a Procedure
Procedure Parameters
Signal Parameters
Default Values
Unconstrained Array Parameters
Summary of Procedure Parameters
Concurrent Procedure Call Statements
Functional Modeling
Pure and Impure Functions
The Function now
Overloading Operator Symbols
Visibility of Declarations
Packages and Use Clauses
Package Declarations
Subprograms in Package Declarations
Constants in Package Declarations
Package Bodies
Local Packages
Use Clauses
Visibility of Used Declarations
Resolved Signals
Basic Resolved Signals
Composite Resolved Subtypes
Summary of Resolved Subtypes
IEEE std_logic_1164 Resolved Subtypes
Resolved Signals, Ports, and Parameters
Resolved Ports
Driving Value Attribute
Resolved Signal Parameters
Predefined and Standard Packages
The Predefined Packages standard and env
IEEE Standard Packages
Standard VHDL Mathematical Packages
Real Number Mathematical Package
Complex Number Mathematical Package
The std_logic_1164 Multivalue Logic System
Standard Integer Numeric Packages
Package Summary
Operator Overloading Summary
Conversion Function Summary
Strength Reduction Function Summary
Aliases for Data Objects
Aliases for Non-Data Items
Generic Constants
Generic Constants
Components and Configurations
Component Declarations
Component Instantiation
Packaging Components
Configuring Component Instances
Basic Configuration Declarations
Configuring Multiple Levels of Hierarchy
Direct Instantiation of Configured Entities
Generic and Port Maps in Configurations
Deferred Component Binding
Generate Statements
Generating Iterative Structures
Conditionally Generating Structures
Design for Synthesis
Synthesizable Subsets
Use of Data Types
Scalar Types
Composite and Other Types
Interpretation of Standard Logic Values
Modeling Combinational Logic
Modeling Sequential Logic
Modeling Edge-Triggered Logic
Level-Sensitive Logic and Inferring Storage
Modeling State Machines
Modeling Memories
Synthesis Attributes
Case Study: System Design Using the Gumnut Core
Overview of the Gumnut
Instruction Set Architecture
External Interface
The Gumnut Entity Declaration
Instruction and Data Memories
A Digital Alarm Clock
System Design
Synthesizing and Implementing the Alarm Clock
Standard Packages
The Predefined Package standard
The Predefined Package env
The Predefined Package textio
Standard VHDL Mathematical Packages
The math_real Package
The math_complex Package
The std_logic_1164 Multivalue Logic System Package
Standard Integer Numeric Packages
The numeric_bit Package
The numeric_std Package
The numeric_bit_unsigned Package
The numeric_std_unsigned Package
VHDL Syntax
Design File
Library Unit Declarations
Declarations and Specifications
Type Definitions
Concurrent Statements
Sequential Statements
Interfaces and Associations
Expressions and Names
Answers to Exercises