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Logical Effort Designing Fast CMOS Circuits

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ISBN-10: 1558605576

ISBN-13: 9781558605572

Edition: 1999

Authors: Ivan E. Sutherland, Robert F. Sproull, David Harris

List price: $81.95
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Logical effort is a simple way of estimating delay in CMOS (complementary metal-oxide semiconductor) gates to design fast circuits. This book offers a practical introduction to the topic.
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Book details

List price: $81.95
Copyright year: 1999
Publisher: Elsevier Science & Technology Books
Publication date: 2/2/1999
Binding: Paperback
Pages: 256
Size: 7.25" wide x 9.50" long x 0.75" tall
Weight: 0.990
Language: English

The Method of Logical Effort
Design Examples
Deriving the Method of Logical Effort
Calculating the Logical Effort of Gates
Calibrating the Model
Asymmetric Logic Gates
Unequal Rising and Falling Delays
Circuit Families
Forks of Amplifiers
Branches and Interconnect
Wide Structures
Conclusions
Cast of Characters
Reference process parameters
Logical Effort Tools
Solutions