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Compilers and Operating Systems for Low Power

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ISBN-10: 1402075731

ISBN-13: 9781402075735

Edition: 2003

Authors: Luca Benini, Mahmut Kandemir, J. Ramanujam, Mahmut Kandemir, J. Ramanujam

List price: $169.00
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Description:

Compilers and Operating Systems for Low Power focuses on both application-level compiler directed energy optimization and low-power operating systems. Chapters have been written exclusively for this volume by several of the leading researchers and application developers active in the field. The first six chapters focus on low energy operating systems, or more in general, energy-aware middleware services. The next five chapters are centered on compilation and code optimization. Finally, the last chapter takes a more general viewpoint on mobile computing. The material demonstrates the state-of-the-art work and proves that to obtain the best energy/performance characteristics, compilers,…    
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Book details

List price: $169.00
Copyright year: 2003
Publisher: Springer
Publication date: 9/30/2003
Binding: Hardcover
Pages: 223
Size: 6.25" wide x 9.25" long x 0.75" tall
Weight: 1.342
Language: English

List of Figures
List of Tables
Contributing Authors
Preface
Low Power Operating System for Heterogeneous Wireless Communication System
Introduction
Event-driven versus General-purpose OS
PicoRadio II Protocol Design
General-purpose Multi-tasking OS
Event-driven OS
Comparison Summary
Low Power Reactive OS for Heterogeneous Architectures
Event-driven Global Scheduler and Power Management
TinyOS Limitations and Proposed Extensions
Conclusion and Future Work
References
A Modified Dual-Priority Scheduling Algorithm for Hard Real-Time Systems to Improve Energy Savings
Introduction
Dual-Priority Scheduling
Power-Low Modified Dual-Priority Scheduling
Experimental Results
Summary
References
Toward the Placement of Power Management Points in Real-Time Applications
Introduction
Model
Sources of Overhead
Computing the New Speed
Setting the New Speed
Speed Adjustment Schemes
Proportional Dynamic Power Management
Dynamic Greedy Power Management
Evaluation of Power Management Schemes
Optimal Number of PMPs
Evaluation of the Analytical Model
Conclusion
Derivation of Formulas
References
Energy Characterization of Embedded Real-Time Operating Systems
Introduction
Related Work
System Overview
The Hardware Platform
RTOS overview
Characterization Strategy
RTOS Characterization Results
Kernel Services
I/O Drivers
Burstiness Test
Clock Speed Test
Resource Contention Test
Application Example: RTOS vs Stand-alone
Cache Related Effects in Thread Switching
Summary of Findings
Conclusions
References
Dynamic Cluster Reconfiguration for Power and Performance
Motivation
Cluster Configuration and Load Distribution
Overview
Implementations
Methodology
Experimental Results
Related Work
Conclusions
References
Energy Management of Virtual Memory on Diskless Devices
Introduction
Related Work
Problem Formulation
EEL[subscript RM] Prototype Compiler
Phase 1 - Analysis
Phase 2 - Code Generation
Performance Model
Example
Implementation Issues
Experiments
Benchmark Characteristics
Simulation Results
Future Work
Conclusion
References
Propagating Constants Past Software to Hardware Peripherals on Fixed-Application Embedded Systems
Introduction
Example
Parameters in Cores
Propagating Constants from Software to Hardware
Experiments
8255A Programmable Peripheral Interface
8237A DMA Controller
PC16550A UART
Free-DCT-L Core
Results
Future Work
Conclusions
References
Constructive Timing Violation for Improving Energy Efficiency
Introduction
Low Power via Fault-Tolerance
Evaluation Methodology
Simulation Results
Related Work
Conclusion and Future Work
References
Power Modeling and Reduction of VLIW Processors
Introduction
Cycle-Accurate VLIW Power Simulation
IMPACT Architecture Framework
Power Models
PowerImpact
Clock Ramping
Clock Ramping with Hardware Prescan (CRHP)
Clock Ramping with Compiler-based Prediction (CRCP)
Basic CRCP Algorithm
Reduction of Redundant Ramp-up Instructions
Control Flow
Load Instructions
Experimental Results
Conclusions and Discussion
References
Low-Power Design of Turbo Decoder with Exploration of Energy-Throughput Trade-off
Introduction
Data Transfer and Storage Exploration Methodology
Global Data Flow and Loop Transformations
Removal of Interleaver Memory
Enabling Parallelism
Storage Cycle Budget Distribution
Memory Hierarchy Layer Assignment
Data Restructuring
Loop Transformations for Parallelization
Loop Merging
Loop Pipelining
Partial Loop Unrolling
Loop Transformation Results
Storage Bandwidth Optimization
Memory Organization
Memory Organization Exploration
Memory Organization Decision
Conclusions
References
Static Analysis of Parameterized Loop Nests for Energy Efficient Use of Data Caches
Introduction
Energy and Line Size
Background
The Parameterized Loop Analysis
Reduction to Single Reference Interference
Interference and Reuse Trade-off
STAMINA Implementation Results
Swim from SPEC 2000
Self Interference
Tiling and Matrix Multiply
Summary and Future Work
References
A Fresh Look at Low-Power Mobile Computing
Introduction
Architecture
Handover and the Quantization of Computational Resources
Standardization of Execution Environment's Parameters
A Commercial Vision: Impact on Billing, Customer Loyalty and Churn
Segmentation of Functionality: The XU-MS Split
Use of Field-Programmable Hardware in the Mobile Station
Special End-To-End Application Requirements
Status and Research Vision
References
Index