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List of Figures | |
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List of Tables | |
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Contributing Authors | |
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Preface | |
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Low Power Operating System for Heterogeneous Wireless Communication System | |
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Introduction | |
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Event-driven versus General-purpose OS | |
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PicoRadio II Protocol Design | |
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General-purpose Multi-tasking OS | |
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Event-driven OS | |
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Comparison Summary | |
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Low Power Reactive OS for Heterogeneous Architectures | |
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Event-driven Global Scheduler and Power Management | |
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TinyOS Limitations and Proposed Extensions | |
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Conclusion and Future Work | |
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References | |
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A Modified Dual-Priority Scheduling Algorithm for Hard Real-Time Systems to Improve Energy Savings | |
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Introduction | |
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Dual-Priority Scheduling | |
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Power-Low Modified Dual-Priority Scheduling | |
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Experimental Results | |
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Summary | |
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References | |
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Toward the Placement of Power Management Points in Real-Time Applications | |
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Introduction | |
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Model | |
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Sources of Overhead | |
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Computing the New Speed | |
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Setting the New Speed | |
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Speed Adjustment Schemes | |
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Proportional Dynamic Power Management | |
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Dynamic Greedy Power Management | |
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Evaluation of Power Management Schemes | |
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Optimal Number of PMPs | |
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Evaluation of the Analytical Model | |
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Conclusion | |
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Derivation of Formulas | |
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References | |
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Energy Characterization of Embedded Real-Time Operating Systems | |
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Introduction | |
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Related Work | |
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System Overview | |
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The Hardware Platform | |
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RTOS overview | |
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Characterization Strategy | |
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RTOS Characterization Results | |
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Kernel Services | |
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I/O Drivers | |
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Burstiness Test | |
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Clock Speed Test | |
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Resource Contention Test | |
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Application Example: RTOS vs Stand-alone | |
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Cache Related Effects in Thread Switching | |
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Summary of Findings | |
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Conclusions | |
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References | |
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Dynamic Cluster Reconfiguration for Power and Performance | |
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Motivation | |
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Cluster Configuration and Load Distribution | |
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Overview | |
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Implementations | |
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Methodology | |
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Experimental Results | |
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Related Work | |
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Conclusions | |
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References | |
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Energy Management of Virtual Memory on Diskless Devices | |
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Introduction | |
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Related Work | |
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Problem Formulation | |
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EEL[subscript RM] Prototype Compiler | |
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Phase 1 - Analysis | |
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Phase 2 - Code Generation | |
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Performance Model | |
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Example | |
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Implementation Issues | |
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Experiments | |
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Benchmark Characteristics | |
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Simulation Results | |
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Future Work | |
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Conclusion | |
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References | |
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Propagating Constants Past Software to Hardware Peripherals on Fixed-Application Embedded Systems | |
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Introduction | |
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Example | |
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Parameters in Cores | |
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Propagating Constants from Software to Hardware | |
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Experiments | |
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8255A Programmable Peripheral Interface | |
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8237A DMA Controller | |
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PC16550A UART | |
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Free-DCT-L Core | |
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Results | |
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Future Work | |
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Conclusions | |
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References | |
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Constructive Timing Violation for Improving Energy Efficiency | |
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Introduction | |
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Low Power via Fault-Tolerance | |
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Evaluation Methodology | |
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Simulation Results | |
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Related Work | |
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Conclusion and Future Work | |
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References | |
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Power Modeling and Reduction of VLIW Processors | |
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Introduction | |
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Cycle-Accurate VLIW Power Simulation | |
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IMPACT Architecture Framework | |
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Power Models | |
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PowerImpact | |
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Clock Ramping | |
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Clock Ramping with Hardware Prescan (CRHP) | |
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Clock Ramping with Compiler-based Prediction (CRCP) | |
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Basic CRCP Algorithm | |
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Reduction of Redundant Ramp-up Instructions | |
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Control Flow | |
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Load Instructions | |
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Experimental Results | |
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Conclusions and Discussion | |
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References | |
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Low-Power Design of Turbo Decoder with Exploration of Energy-Throughput Trade-off | |
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Introduction | |
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Data Transfer and Storage Exploration Methodology | |
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Global Data Flow and Loop Transformations | |
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Removal of Interleaver Memory | |
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Enabling Parallelism | |
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Storage Cycle Budget Distribution | |
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Memory Hierarchy Layer Assignment | |
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Data Restructuring | |
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Loop Transformations for Parallelization | |
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Loop Merging | |
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Loop Pipelining | |
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Partial Loop Unrolling | |
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Loop Transformation Results | |
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Storage Bandwidth Optimization | |
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Memory Organization | |
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Memory Organization Exploration | |
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Memory Organization Decision | |
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Conclusions | |
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References | |
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Static Analysis of Parameterized Loop Nests for Energy Efficient Use of Data Caches | |
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Introduction | |
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Energy and Line Size | |
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Background | |
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The Parameterized Loop Analysis | |
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Reduction to Single Reference Interference | |
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Interference and Reuse Trade-off | |
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STAMINA Implementation Results | |
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Swim from SPEC 2000 | |
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Self Interference | |
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Tiling and Matrix Multiply | |
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Summary and Future Work | |
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References | |
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A Fresh Look at Low-Power Mobile Computing | |
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Introduction | |
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Architecture | |
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Handover and the Quantization of Computational Resources | |
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Standardization of Execution Environment's Parameters | |
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A Commercial Vision: Impact on Billing, Customer Loyalty and Churn | |
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Segmentation of Functionality: The XU-MS Split | |
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Use of Field-Programmable Hardware in the Mobile Station | |
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Special End-To-End Application Requirements | |
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Status and Research Vision | |
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References | |
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Index | |