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Low-Voltage CMOS Log Companding Analog Design

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ISBN-10: 140207445X

ISBN-13: 9781402074455

Edition: 2003

Authors: Francisco Serra-Graells, Adoraci�n Rueda, Jos� L. Huertas

List price: $109.99
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Low-Voltage CMOS Log Companding Analog Design presents in detail state-of-the-art analog circuit techniques for the very low-voltage and low-power design of systems-on-chip in CMOS technologies. The proposed strategy is mainly based on two bases: the Instantaneous Log Companding Theory, and the MOSFET operating in the subthreshold region. The former allows inner compression of the voltage dynamic-range for very low-voltage operation, while the latter is compatible with CMOS technologies and suitable for low-power circuits. The required background on the specific modeling of the MOS transistor for Companding is supplied at the beginning. Following this general approach, a complete set of…    
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Book details

List price: $109.99
Copyright year: 2003
Publisher: Springer
Publication date: 6/30/2003
Binding: Hardcover
Pages: 192
Size: 6.10" wide x 9.25" long x 0.50" tall
Weight: 2.376
Language: English

List of Figures
List of Tables
Low-Power Applications and CMOS Technologies
State-of-the-Art Low-Power Analog Design
Instantaneous Companding Theory
CMOS Subthreshold Companding Proposal
Structure of this Book
Mosfet Modeling for Companding
Model Requirements for Analytical Design
Large Signal Equations
DC Drain Current
Quasi-Static Capacitances
Small signal Parameters
Noise Equations
Technology Mismatching Model
Parameter Extraction Procedure
Amplification and Agc
Log Companding Principle
CMOS Generalization
Basic Building Blocks
General-Purpose Controllable Amplifier Cell
Low-Impedance Gain Control Voltage Sources
Full-Wave Rectifiers
Envelope Filtering
Log Ruler
Compression Ratio Scaling
Design Examples
Log Companding Principle
CMOS Generalization
Basic Building Blocks
Saturated CMOS Cells
Non-Saturated CMOS Cells
Auxiliary Circuitry
Design Methodology
Case Studies
First-Order Low-Pass
Second-Order Low-Pass
Second-Order Band-Pass
All-MOS Implementations
Design Examples
Ptat Generation
Log Companding Principle
CMOS Generalization
Design Examples
Pulse Duration Modulation
Log Companding Principle
CMOS Generalization
Design Example
Dynamic Range
CMOS Considerations
Moderate Inversion distortion
Noise Floor
Dynamic Range Versus Signal-to-Noise Ratio
Industrial Application: Hearing Aids
History and Market
Previous CMOS Analog Systems
A True 1V CMOS Log-Domain Analog Hearing-Aid-on-Chip
System-on-Chip Specifications
Full-Custom ASIC Implementation
Comparative Results
Yield Issues
Future Work
Simulation and Test
Numerical Simulation
SPICE Models
Numerical Convergence
Large Signal Frequency Analysis
Technology Mismatching Simulation
Experimental Test Setup