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| Foreword | |
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| Preface | |
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| Functional Verification | |
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| Formal Methods for Functional Verification | |
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| Automating the Diagnosis and the Rectification of Design Errors with PRIAM | |
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| Functional Comparison of Logic Designs for VLSI Circuits | |
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| A Unified Framework for the Formal Verification of Sequential Circuits | |
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| Dynamic Variable Ordering for Ordered Binary Decision Diagrams | |
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| Verification of Large Synthesized Designs | |
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| GRASP-A New Search Algorithm for Satisfiability | |
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| System Design and Analysis | |
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| System Design and Analysis Overview | |
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| An Efficient Microcode-Compiler for Custom DSP-Processors | |
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| HYPER-LP: A System for Power Minimization Using Architectural Transformations | |
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| Power Analysis of Embedded Software: First Step Towards Software Power Minimization | |
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| A Methodology for Correct-by-Construction Latency Insensitive Design | |
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| Exploring Performance Tradeoffs for Clustered VLIW ASIPs | |
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| Logic Synthesis | |
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| Logic Synthesis Overview | |
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| Multiple-Level Logic Optimization System | |
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| Exact Minimization of Multiple-Valued Functions for PLA Optimization | |
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| Improved Logic Optimization Using Global-Flow Analysis | |
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| A Method for Concurrent Decomposition and Factorization of Boolean Expressions | |
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| An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs | |
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| Logic Decomposition during Technology Mapping | |
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| Analog and Digital Circuit Design | |
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| Highlights in Analog and Digital Circuit Design and Synthesis at ICCAD | |
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| An Interactive Device Characterization and Model Development System | |
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| TILOS: A Posynomial Programming Approach to Transistor Sizing | |
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| SPECS2: An Integrated Circuit Timing Simulator | |
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| Automatic Synthesis of Operational Amplifiers based on Analytic Circuit Models | |
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| Analog Circuit Synthesis for Performance in OASYS | |
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| Extraction of Gate-Level Models from Transistor Circuits by Four-Valued Symbolic Analysis | |
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| Optimization of Custom MOS Circuits by Transistor Sizing | |
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| Physical Simulation and Analysis | |
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| Highlights in Physical Simulation and Analysis at ICCAD | |
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| Nonlinear Simulation in the Frequency-Domain | |
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| Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation | |
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| Efficient Techniques for Inductance Extraction of Complex 3-D Geometries | |
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| Time-Domain Non-Monte Carlo Noise Simulation for Nonlinear Dynamic Circuits with Arbitrary Excitations | |
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| PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm | |
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| Circuit Noise Evaluation by Pade Approximation Based Model-Reduction Techniques | |
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| Physical Design | |
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| Physical Design Overview | |
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| Floorplan Design Using Annealing | |
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| GOALIE: A Space-Efficient System for VLSI Artwork Analysis | |
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| Gordian: A New Global Optimization/ Rectangle Dissection Method for Cell Placement | |
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| Exact Zero Skew | |
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| Efficient Network Flow Based Min-Cut Balanced Partitioning | |
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| Rectangle-Packing-Based Module Placement | |
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| Timing, Test and Manufacturing | |
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| Timing, Test and Manufacturing Overview | |
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| A Methodology for Worst Case Design of Integrated Circuits | |
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| Timing Analysis using Functional Relationships | |
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| On the Design of Robust Multiple Fault Testable CMOS Combinational Logic Circuits | |
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| Circuit Optimization Driven by Worst-Case Distances | |
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| Verifying Clock Schedules | |
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| Efficient Implementation of Retiming | |
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| Industry Viewpoints | |
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| A Cadence Perspective on ICCAD | |
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| ICCAD and Fujitsu | |
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| ICCAD's Impact in IBM | |
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| Magma and ICCAD | |
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| Designers Face Critical Challenges and Discontinuities of Analog/Mixed Signal Design and Physical Verification | |
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| NEC and ICCAD - EDA partners in success | |
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| The Strong Mutual Impact between Philips Research and the ICCAD | |
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| Contributions from the "Best of ICCAD" to Synopsys | |
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| ICCAD and Xilinx | |
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| Index | |
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| Author Index | |
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| Reference Index | |