High Performance Memory Testing Design Principles, Fault Modeling and Self-Test

Name: High Performance Memory Testing Design Principles, Fault Modeling and Self-Test
Availability: InStock
ISBN: 9781402072550

ISBN-10: 1402072554

ISBN-13: 9781402072550

Edition: 2003

Authors: R. Dean Adams

List price: $169.99

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Description:

Design and test are considered jointly in this book since knowledge of one without the other is insufficient for the task of having high quality memories. Knowledge of memory design is required to understand test. An understanding of test is required to have effective built-in self-test implementations. A poor job can be done on any of these pieces resulting in a memory that passes test but which is not actually good. The relentless press of Moore's law drives more and more bits onto a single chip. The large number of bits means that methods that were "gotten away with" in the past will no longer be sufficient. Because the number of bits is so large, fine nuances of fails that were rarely…

Book details

List price: $169.99
Copyright year: 2003
Publisher: Springer
Publication date: 9/30/2002
Binding: Hardcover
Pages: 250
Size: 6.10" wide x 9.25" long x 1.00" tall
Weight: 2.684
Language: English



Preface



Design & Test of Memories



Opening Pandora's Box



What is a Memory, Test, BIST?



The Ubiquitous Nature of Memories



The Complexity of Memories



It was the best of memories, it was the worst of memories...



Testing: Bits is Not Bits



Best BIST or Bust: The journey toward the best self test



Ignorance is Not Bliss



Conclusions



Static Random Access Memories



SRAM Trends



The Cell



Read Data Path



Write Driver Circuit



Decoder Circuitry



Layout Considerations



Redundancy



Summary



Multi-Port Memories



Cell Basics



Multi-Port Memory Timing Issues



Layout Considerations



Summary



Silicon On Insulator Memories



Silicon On Insulator Technology



Memories in SOI



Layout Considerations



Summary



Content Addressable Memories



CAM Topology



Masking



CAM Features



Summary



Dynamic Random Access Memories



DRAM Trends



The DRAM cell



The DRAM Capacitor



DRAM Cell Layout



DRAM Operation



Conclusions



Non-Volatile Memories



ROM



EEPROM & Flash



The Future of memories



FeRAM



MRAM



Ovonic



And Beyond



Conclusions



Memory Testing



Memory Faults



A Toast: To Good Memories



Fault Modeling



General Fault modeling



Read Disturb Fault Model



Pre-charge Faults



False Write Through



Data Retention Faults



SOI Faults



Decoder Faults



Multi-port Memory Faults



Other Fault Models



Memory Patterns



Zero-One Pattern



Exhaustive Test Pattern



Walking, Marching, and Galloping



Bit and Word Orientation



Common Array Patterns



Common March Patterns



March C- Pattern



Partial Moving Inversion Pattern



Enhanced March C- Pattern



March LR Pattern



March G Pattern



SMarch Pattern



Pseudo-Random Patterns



CAM Patterns



SOI Patterns



Multi-Port Memory Patterns



Summary



Memory Self Test



BIST Concepts



The Memory Boundary



Manufacturing Test and Beyond



ATE and BIST



At-Speed Testing



Deterministic BIST



Pseudo-Random BIST



Conclusions



State Machine BIST



Counters and BIST



A Simple Counter



Read/Write Generation



The BIST Portions



Programming and State Machine BISTs



Complex Patterns



Conclusions



Micro-Code BIST



Micro-code BIST Structure



Micro-code Instructions



Looping and Branching



Using a Micro-coded Memory BIST



Conclusions



BIST and Redundancy



Replace, Not Repair



Redundancy Types



Hard and Soft Redundancy



Challenges in BIST and Redundancy



The Redundancy Calculation



Conclusions



Design For Test and BIST



Weak Write Test Mode



Bit Line Contact Resistance



PFET Test



Shadow Write and Shadow Read



General Memory DFT Techniques



Conclusions



Conclusions



The Right BIST for the Right Design



Memory Testing



The Future of Memory Testing


Appendices



Further Memory Fault Modeling



Linked Faults



Coupling Fault Models



Inversion Coupling Fault



Idempotent Coupling Fault



Complex Coupling Fault



State Coupling Fault



V Coupling Fault



Neighborhood Pattern Sensitive Fault Models Expanded



Pattern Sensitive Fault Model



Active Neighborhood Pattern Sensitive Fault Model



Passive Neighborhood Pattern Sensitive Fault Model



Static Neighborhood Pattern Sensitive Fault Model



Recovery Fault Models



Sense Amplifier Recovery Fault Model



Write Recovery Fault Model



Slow write Recovery Fault Model



Stuck Open Fault Models



Stuck Open Cell Fault Model



Stuck Open Bit Line Fault Model



Imbalanced Bit Line Fault Model



Multi-Port Memory Faults



Further Memory Test Patterns



MATS Patterns



MATS



MATS+



MATS++



Marching 1/0



Lettered March Patterns



March A



March B



March C



March X



March Y



March C+, C++, A+, A++ Patterns



March LA



March SR+



IFA Patterns



9N Linear



13N



Other Patterns



MovC



Moving Inversion



Butterfly



SMARCH



Pseudo-Random



State Machine HDL


References


Glossary / Acronyms


Index


About the Author