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Reuse Methodology Manual for System-on-a-Chip Designs

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ISBN-10: 1402071418

ISBN-13: 9781402071416

Edition: 3rd 2002 (Revised)

Authors: Michael Keating, Pierre Bricaud

List price: $139.00
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Description:

Reuse Methodology Manual for System-on-a-Chip Designs, Third Edition outlines a set of best practices for creating reusable designs for use in an SoC design methodology. These practices are based on the authors' experience in developing reusable designs, as well as the experience of design teams in many companies around the world. Silicon and tool technologies move so quickly that many of the details of design-for-reuse will undoubtedly continue to evolve over time. But the fundamental aspects of the methodology described in this book have become widely adopted and are likely to form the foundation of chip design for some time to come. Development methodology necessarily differs between…    
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Book details

List price: $139.00
Edition: 3rd
Copyright year: 2002
Publisher: Springer
Publication date: 6/30/2002
Binding: Hardcover
Pages: 330
Size: 6.25" wide x 9.25" long x 0.75" tall
Weight: 1.430
Language: English

Foreword
Preface to the Third Edition
Acknowledgements
Introduction
Goals of This Manual
Assumptions
Definitions
Virtual Socket Interface Alliance
Design for Reuse: The Challenge
Design for Use
Design for Reuse
The Emerging Business Model for Reuse
The System-on-Chip Design Process
A Canonical SoC Design
System Design Flow
Waterfall vs. Spiral
Top-Down vs. Bottom-Up
Construct by Correction
Summary
The Specification Problem
Specification Requirements
Types of Specifications
The System Design Process
System-Level Design Issues: Rules and Tools
The Standard Model
Soft IP vs. Hard IP
The Role of Full-Custom Design in Reuse
Design for Timing Closure: Logic Design Issues
Interfaces and Timing Closure
Synchronous vs. Asynchronous Design Style
Clocking
Reset
Timing Exceptions and Multicycle Paths
Design for Timing Closure: Physical Design Issues
Floorplanning
Synthesis Strategy and Timing Budgets
Hard Macros
Clock Distribution
Design for Verification: Verification Strategy
System Interconnect and On-Chip Buses
Basic Interface Issues
Tristate vs. Mux Buses
Synchronous Design of Buses
Summary
IP-to-IP Interfaces
Design for Bring-Up and Debug: On-Chip Debug Structures
Design for Low Power
Lowering the Supply Voltage
Reducing Capacitance and Switching Activity
Sizing and Other Synthesis Techniques
Summary
Design for Test: Manufacturing Test Strategies
System-Level Test Issues
Memory Test
Microprocessor Test
Other Macros
Logic BIST
Prerequisites for Reuse
Libraries
Physical Design Rules
The Macro Design Process
Overview of IP Design
Characteristics of Good IP
Implementation and Verification IP
Overview of Design Process
Key Features
Planning and Specification
Functional Specification
Verification Specification
Packaging Specification
Development Plan
High-Level Models as Executable Specifications
Macro Design and Verification
Summary
Soft Macro Productization
Productization Process
Activities and Tools
RTL Coding Guidelines
Overview of the Coding Guidelines
Basic Coding Practices
General Naming Conventions
Naming Conventions for VITAL Support
State Variable Names
Include Informational Headers in Source Files
Use Comments
Keep Commands on Separate Lines
Line Length
Indentation
Do Not Use HDL Reserved Words
Port Ordering
Port Maps and Generic Maps
VHDL Entity, Architecture, and Configuration Sections
Use Functions
Use Loops and Arrays
Use Meaningful Labels
Coding for Portability
Use Only IEEE Standard Types (VHDL)
Do Not Use Hard-Coded Numeric Values
Packages (VHDL)
Constant Definition Files (Verilog)
Avoid Embedding Synthesis Commands
Use Technology-Independent Libraries
Coding For Translation
Guidelines for Clocks and Resets
Avoid Mixed Clock Edges
Avoid Clock Buffers
Avoid Gated Clocks
Avoid Internally Generated Clocks
Gated Clocks and Low-Power Designs
Avoid Internally Generated Resets
Reset Logic Function
Single-Bit Synchronizers
Multiple-Bit Synchronizers
Coding for Synthesis
Infer Registers
Avoid Latches
If you must use a latch
Avoid Combinational Feedback
Specify Complete Sensitivity Lists
Blocking and Nonblocking Assignments (Verilog)
Signal vs. Variable Assignments (VHDL)
Case Statements vs. if-then-else Statements
Coding Sequential Logic
Coding Critical Signals
Avoid Delay Times
Avoid ful_case and parallel_case Pragmas
Partitioning for Synthesis
Register All Outputs
Locate Related Combinational Logic in a Single Module
Separate Modules That Have Different Design Goals
Asynchronous Logic
Arithmetic Operators: Merging Resources
Partitioning for Synthesis Runtime
Avoid Timing Exceptions
Eliminate Glue Logic at the Top Level
Chip-Level Partitioning
Designing with Memories
Code Profiling
Macro Synthesis Guidelines
Overview of the Synthesis Problem
Macro Synthesis Strategy
Macro Timing Constraints
Subblock Timing Constraints
Synthesis in the Design Process
Subblock Synthesis Process
Macro Synthesis Process
Wire Load Models
Preserve Clock and Reset Networks
Code Checking Before Synthesis
Code Checking After Synthesis
Physical Synthesis
Classical Synthesis
Physical Synthesis
Physical Synthesis Deliverables
RAM and Datapath Generators
Memory Design
RAM Generator Flow
Datapath Design
Coding Guidelines for Synthesis Scripts
Macro Verification Guidelines
Overview of Macro Verification
Verification Plan
Verification Strategy
Inspection as Verification
Adversarial Testing
Testbench Design
Transaction-Based Verification
Component-Based Verification
Automated Response Checking
Verification Suite Design
Design of Verification Components
Bus Functional Models
Monitors
Device Models
Verification Component Usage
Getting to 100%
Functional and Code Coverage
Prototyping
Limited Production
Property Checking
Code Coverage Analysis
Timing Verification
Developing Hard Macros
Overview
Why and When to Use Hard Macros
Design Process for Hard vs. Soft Macros
Design Issues for Hard Macros
Full-Custom Design
Interface Design
Design For Test
Clock
Aspect Ratio
Porosity
Pin Placement and Layout
Power Distribution
Antenna Checking
The Hard Macro Design Process
Productization of Hard Macros
Physical Design
Verification
Model Development for Hard Macros
Functional Models
Timing Models
Power Models
Test Models
Physical Models
Porting Hard Macros
Macro Deployment: Packaging for Reuse
Delivering the Complete Product
Soft Macro Deliverables
Hard Macro Deliverables
Software
The Design Archive
Contents of the User Guide
System Integration with Reusable Macros
Integration Overview
Integrating Macros into an SoC Design
Problems in Integrating IP
Strategies for Managing Interfacing Issues
Interfacing Hard Macros to the Rest of the Design
Selecting IP
Hard Macro Selection
Soft Macro Selection
Soft Macro Installation
Soft Macro Configuration
Synthesis of Soft Macros
Integrating Memories
Physical Design
Design Planning and Synthesis
Physical Placement
Timing Closure
Verifying the Physical Design
Summary
System-Level Verification Issues
The Importance of Verification
The Verification Strategy
Interface Verification
Transaction Verification
Data or Behavioral Verification
Standardized Interfaces
Functional Verification
Random Testing
Application-Based Verification
Software-Driven Application Testbench
Rapid Prototyping for Testing
Gate-Level Verification
Sign-Off Simulation
Formal Verification
Gate-Level Simulation with Full Timing
Specialized Hardware for System Verification
Accelerated Verification Overview
RTL Acceleration
Software Driven Verification
Traditional In-Circuit Verification
Design Guidelines for Emulation
Testbenches for Emulation
Data and Project Management
Data Management
Revision Control Systems
Bug Tracking
Regression Testing
Managing Multiple Sites
Archiving
Project Management
Development Process
Functional Specification
Project Plan
Implementing Reuse-Based SoC Designs
Alcatel
Atmel
Infineon Technologies
LSI Logic
Philips Semiconductor
STMicroelectronics
Conclusion
Bibliography
Index