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| System Level Design | |
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| System Level Design: Past, Present, and Future | |
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| Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems | |
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| EXPRESSION: A Language for Architecture Exploration Through Compiler/Simulator Retargetability | |
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| RTOS Modeling for System Level Design | |
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| Context-Aware Performance Analysis for Efficient Embedded System Design | |
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| Lock-Free Synchronization for Dynamic Embedded Real-Time Systems | |
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| What If You Could Design Tomorrow's System Today? | |
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| Networks on Chip | |
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| Networks on Chips | |
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| A Generic Architecture for On-Chip Packet-Switched Interconnections | |
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| Trade-offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip | |
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| Exploiting the Routing Flexibility for Energy/Performance-Aware Mapping of Regular NoC Architectures | |
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| XpipesCompiler: A Tool for Instantiating Application- Specific Networks on Chip | |
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| A Network Traffic Generator Model for Fast Network-on-Chip Simulation | |
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| Modeling, Simulation and Run-Time Management | |
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| Modeling, Simulation and Run-Time Management | |
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| Dynamic Power Management for Nonstationary Service Requests | |
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| Quantitative Comparison of Power Management Algorithms | |
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| Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives | |
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| Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application | |
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| Compositional Specification of Behavioral Semantics | |
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| Design Technology For Advanced Digital Systems in CMOS and Beyond | |
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| Design Technology for Advanced Digital Systems in CMOS and Beyond | |
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| Address Bus Encoding Techniques for System-Level Power Optimization | |
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| MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis | |
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| Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processors | |
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| Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies | |
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| Physical Design and Validation | |
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| Physical Design and Validation | |
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| Interconnect Tuning Strategies for High-Performance ICs | |
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| Efficient Inductance Extraction via Windowing | |
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| Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits | |
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| A Single Photon Avalanche Diode Array Fabricated in Deep-Submicron CMOS Technology | |
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| Test and Verification | |
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| The Test and Verification Influential Papers in the 10 Years of DATE | |
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| Cost Reduction and Evaluation of a Temporary Faults-Detecting Technique | |
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| An Integrated System-on-Chip Test Framework | |
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| Efficient Spectral Techniques for Sequential ATPG | |
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| BerkMin: A Fast and Robust Sat-Solver | |
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| Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-Chip Test Data Compression/Decompression | |
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| An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs | |
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| Shortlist of Most Influential Papers | |