Logic Synthesis and Verification Algorithms

ISBN-10: 0792397460

ISBN-13: 9780792397465

Edition: 1996

List price: $99.00
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Description:

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics. A unique feature of this text is the large collection of solved problems. Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.
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Book details

List price: $99.00
Copyright year: 1996
Publisher: Springer
Publication date: 6/30/1996
Binding: Hardcover
Pages: 564
Size: 7.00" wide x 10.00" long x 1.00" tall
Weight: 2.882
Language: English

Introduction
Introduction
A Quick Tour of Logic Synthesis with the Help of a Simple Example
Two Level Logic Synthesis
Boolean Algebras
Synthesis of Two-Level Circuits
Heuristic Minimization of Two-Level Circuits
Binary Decision Diagrams (BDDs)
Models of Sequential Systems
Models of Sequential Systems
Synthesis and Verification of Finite State Machines
Finite Automata
Multilevel Logic Synthesis
Multi-Level Logic Synthesis
Multi-Level Minimization
Automatic Test Generation for Combinational Circuits
Technology Mapping
ASCII Codes
Supplementary Problems
Bibliography
Index
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