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| Preface | |
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| Basic Principles of Digital Systems | |
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| Digital Versus Analog Electronics | |
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| Digital Logic Levels | |
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| The Binary Number System | |
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| Hexadecimal Numbers | |
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| Digital Waveforms | |
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| Logic Functions and Gates | |
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| Basic Logic Functions | |
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| Logic Switches and LED Indicators | |
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| Derived Logic Functions | |
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| DeMorgan's Theorems and Gate Equivalence | |
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| Enable and Inhibit Properties of Logic Gates | |
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| Integrated Circuit Logic Gates | |
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| Boolean Algebra and Combinational Logic | |
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| Boolean Expressions, Logic Diagrams and Truth Tables | |
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| Sum-of-Products (SOP) and Product-of-Sums (POS) Forms | |
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| Theorems of Boolean Algebra | |
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| Simplifying SOP and POS Expressions | |
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| Simplification by the Karnaugh Map Method | |
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| Introduction to PLDs and MAX+PLUS II | |
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| What is a PLD? | |
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| Programming PLDs using MAX+PLUS II | |
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| Graphic Design File | |
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| Compling MAX+PLUS II Files | |
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| Hierarchical Design | |
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| Text Design File (VHDL) | |
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| Creating a Physical Design | |
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| Combinational Logic Functions | |
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| Decoders | |
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| Encoders | |
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| Multiplexers | |
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| Demultiplexers | |
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| Magnitude Comparators | |
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| Parity Generators and Checkers | |
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| Digital Arithmetic and Arithmetic Circuits | |
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| Digital Arithmetic | |
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| Representing Signed Binary Numbers | |
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| Signed Binary Arithmetic | |
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| Hexadecimal Arithmetic | |
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| Numeric and Alphanumeric Codes | |
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| Binary Adders and Subtractors | |
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| BCD Adders | |
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| Carry Generation in MAX+PLUS II | |
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| Introduction to Sequential Logic | |
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| Latches | |
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| NAND/NOR Latches | |
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| Gated Latches | |
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| Edge-Triggered D Flip-Flops | |
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| Edge-Triggered JK Flip-Flops | |
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| Edge-Triggered T Flip-Flops | |
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| Timing Parameters | |
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| Introduction to Programmable Logic Architectures | |
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| Programmable Sum-of-Products Arrays | |
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| PAL Fuse Matrix and Combinational Outputs | |
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| PAL Outputs with Programmable Polarity | |
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| PAL Devices with Registered Outputs | |
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| Universal PAL and Generic Array Logic | |
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| MAX7000S CPLD | |
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| FLEX10K CPLD | |
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| Counters and Shift Registers | |
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| Basic Concepts of Digital Counters | |
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| Synchronous Counters | |
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| Design of Synchronous Counters | |
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| Programming Binary Counters in VHDL | |
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| Control Options for Synchronous Counters | |
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| Programming Presettable and Bidirectional Counters in VHDL | |
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| Shift Registers | |
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| Programming Shift Registers in VHDL | |
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| Shift Register Counters | |
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| State Machine Design | |
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| State Machines | |
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| State Machines With No Control Inputs | |
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| State Machines With Control Inputs | |
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| Switch Debouncer for a Normally Open Pushbutton Switch | |
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| Unused States in State Machines | |
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| Traffic Light Controller | |
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| Logic Gate Circuitry | |
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| Electrical Characteristics of Logic Gates | |
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| Propagation Delay | |
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| Fanout | |
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| Power Dissipation | |
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| Noise Margin | |
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| Interfacing TTL and CMOS Gates | |
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| Internal Circuitry of TTL gates | |
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| Internal Circuitry of CMOS Gates | |
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| TTL and CMOS Variations | |
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| Interfacing Analog and Digital Circuitry | |
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| Analog and Digital Signals | |
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| Digital-to-Analog Conversion | |
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| Analog-to-Digital Conversion | |
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| Data Acquisition | |
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| Memory Devices and Systems | |
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| Basic Memory Concepts | |
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| Random Access Read/Write Memory (RAM) | |
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| Read Only Memory (ROM) | |
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| Sequential Memory: FIFO and LIFO | |
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| Dynamic RAM Modules | |
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| Memory Systems | |
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| Altera UP-1 User's Guide | |
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| VHDL Language Reference | |
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| Data Sheets | |
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| CMOS Handling Precautions | |
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| EPROM/ROM Data for a Digital Function Generator | |
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| Answers to Selected Odd-Numbered Problems | |
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| Index | |