ISBN-10: 0750689749

ISBN-13: 9780750689748

Edition: 2008

Authors: Clive Maxfield

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FPGAs are central to electronic design! The engineers designing these devices are in need of essential information at a moment's notice. The Instant Access Series provides all the critical content that a computer design engineer needs in his or her daily work. This book provides an introduction to FPGAs as well as succinct overviews of fundamental concepts and basic programming. FPGAs are a customizable chip flexible enough to be deployed in a wide range of products and applications. There are several basic design flows detailed including ones based in C/C++, DSP, and HDL. This book is filled with images, figures, tables, and easy to find tips and tricks for the engineer that needs material fast to complete projects to deadline. *Tips and tricks feature that will help engineers get info fast and move on to the next issue *Easily searchable content complete with tabs, chapter table of contents, bulleted lists, and boxed features *Just the essentials, no need to page through material not needed for the current project
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Book details

List price: $49.95
Copyright year: 2008
Publisher: Elsevier Science & Technology Books
Publication date: 7/28/2008
Binding: Paperback
Pages: 216
Size: 5.75" wide x 8.75" long x 0.25" tall
Weight: 0.638
Language: English

Clive "Max" Maxfield received a BS in Control Engineering from Sheffield Polytechnic, England in 1980. He began his career as a mainframe CPU designer for International Computers Limited (ICL) in Manchester, England. Max now finds himself a member of the technical staff (MTS) at Intergraph Electronics, Huntsville, Alabama. Max is the author of dozens of articles and papers appearing in magazines and at technical conferences around the world. Max's main area of interest are currently focused in the analog, digital, and mixed-signal simulation of integrated circuits and multichip modules.

About the Author
The Fundamentals
Why Use FPGAs?
Some Technology Background
Fusible-link Technology
FPGA Programming Technologies
Instant Summary
FPGA Architectures
More on Programming Technologies
SRAM-based Devices
Antifuse-based Devices
E[superscript 2]PROM/FLASH-based Devices
Hybrid FLASH-SRAM Devices
Fine-, Medium-, and Coarse-grained Architectures
Logic Blocks
LUT versus Distributed RAM versus SR
CLBs versus LABs versus Slices
Logic Cells/Logic Elements
Slicing and Dicing
CLBs and LABs
Distributed RAMs and Shift Registers
Embedded RAMs
Embedded Multipliers, Adders, etc.
Embedded Processor Cores
Hard Microprocessor Cores
Soft Microprocessor Cores
Clock Managers
Clock Trees
Clock Managers
General-purpose I/O
Configurable I/O Standards
Configurable I/O Impedances
Core versus I/O Supply Voltages
Gigabit Transceivers
Multiple Standards
Intellectual Property (IP)
Handcrafted IP
IP Core Generators
System Gates versus Real Gates
Instant Summary
Programming (Configuring) an FPGA
Configuration Cells
Antifuse-based FPGAs
SRAM-based FPGAs
Programming Embedded (Block) RAMs, Distributed RAMs, etc.
Multiple Programming Chains
Quickly Reinitializing the Device
Using the Configuration Port
Serial Load with FPGA as Master
Parallel Load with FPGA as Master
Parallel Load with FPGA as Slave
Serial Load with FPGA as Slave
Using the JTAG Port
Using an Embedded Processor
Instant Summary
FPGA vs. ASIC Designs
When You Switch from ASIC to FPGA Design, or Vice Versa
Coding Styles
Pipelining and Levels of Logic
Levels of Logic
Asynchronous Design Practices
Asynchronous Structures
Combinational Loops
Delay Chains
Clock Considerations
Clock Domains
Clock Balancing
Clock Gating versus Clock Enabling
PLLs and Clock Conditioning Circuitry
Reliable Data Transfer across Multiclock Domains
Register and Latch Considerations
Flip-flops with both "Set" and "Reset" Inputs
Global Resets and Initial Conditions
Resource Sharing (Time-Division Multiplexing)
Use It or Lose It!
But Wait, There's More
State Machine Encoding
Test Methodologies
Migrating ASIC Designs to FPGAs and Vice Versa
Alternative Design Scenarios
Instant Summary
"Traditional" Design Flows
Schematic-based Design Flows
Back-end Tools like Layout
A Simple (early) Schematic-driven ASIC Flow
A Simple (early) Schematic-driven FPGA Flow
Flat versus Hierarchical Schematics
Schematic-driven FPGA Design Flows Today
HDL-based Design Flows
Advent of HDL-based Flows
A Plethora of HDLs
Points to Ponder
Instant Summary
Other Design Flows
C/C++-based Design Flows
C versus C++ and Concurrent versus Sequential
SystemC-based Flows
Augmented C/C++-based Flows
Pure C/C++-based Flows
Different Levels of Synthesis Abstraction
Mixed-language Design and Verification Environments
DSP-Based Design Flows
Alternative DSP Implementations
FPGA-centric Design Flows for DSPs
Mixed DSP and VHDL/Verilog etc. Environments
Embedded Processor-based Design Flows
Hard versus Soft Cores
Partitioning a Design into Its Hardware and Software Components
Using an FPGA as Its Own Development Environment
Improving Visibility in the Design
A Few Coverification Alternatives
Instant Summary
Using Design Tools
Simulation Tools
Event-driven Logic Simulators
Logic Values and Different Logic Value Systems
Mixed-language Simulation
Alternative Delay Formats
Cycle-based Simulators
Choosing a Logic Simulator
Synthesis (Logic/HDL versus Physically Aware)
Logic/HDL Synthesis Technology
Physically Aware Synthesis Technology
Retiming, Replication, and Resynthesis
Timing Analysis
Static Timing Analysis
Statistical Static Timing Analysis
Verification in General
Verification IP
Verification Environments and Creating Testbenches
Analyzing Simulation Results
Formal Verification
Different Flavors of Formal Verification
Terminology and Definitions
Alternative Assertion/Property Specification Techniques
Static Formal versus Dynamic Formal
HDL to C Conversion
Code Coverage
Performance Analysis
Instant Summary
Choosing the Right Device
Basic Resources and Packaging
General-purpose I/O Interfaces
Embedded Multipliers, RAMs, etc.
Embedded Processor Cores
Gigabit I/O Capabilities
IP Availability
Speed Grades
Future FPGA Developments
Instant Summary
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