Analysis and Design of Digital Systems with VHDL

Name: Analysis and Design of Digital Systems with VHDL
Price: 8.2 USD
Availability: InStock
ISBN: 9780534954109

ISBN-10: 0534954103

ISBN-13: 9780534954109

Edition: 1st 1997

Authors: Allen M. Dewey

List price: $277.95

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ANALYSIS AND DESIGN OF DIGITAL SYSTEMS WITH VHDL integrates industry-standard hardware description language (VHDL) technology into the undergraduate digital logic course. Author Allen Dewey observes that the widespread use of VHDL in specifying digital system designs is driving change and innovation in industry, and defining a new skill set that engineering students must master to design, model, communicate, and implement digital systems. VHDL provides a formal mechanism for describing digital systems in a format easily processed by computers, succinctly capturing the basic concepts of digital systems engineering and harnessing the power of design automation technology. This book first…

Book details

List price: $277.95
Edition: 1st
Copyright year: 1997
Publisher: Course Technology
Publication date: 8/26/1996
Binding: Digital, Other
Pages: 704
Size: 8.50" wide x 10.50" long x 1.25" tall
Weight: 3.234
Language: English



Preface



Introduction


Electronic Systems


Digital Systems


Digital System Design Process


Design Automation


VHDL


Summary



Representing Information


Representing Positive Numbers in Binary


Converting Between Binary and Decimal


Binary Arithmetic


Representing Negative Numbers in Binary


Octal and Hexadecimal Number Systems


Binary Codes


Representing Characters in Binary


Summary


Problems



Digital Engineering: Combinational Systems



Combinational Systems: Definition And Analysis


Overview of Combinational Systems


Switching Algebra


Additional Logic Operations


Logic Mnemonics


Minimal Sets of Logic Operators


Multi-Input Logic Operator


Combinational System Analysis


Logic Expressions


Documenting Combinational Systems


Combinational System Analysis: A Second Look


Summary


Problems



Combinational Design: Synthesis


Generating Logic Expressions from Prose


Minimization Techniques


Algebraic Minimization Technique


Karnaugh Map Minimization Technique


Quine-McCluskey Minimization Technique


Exercise: Weather Vane


Summary


Problems



Combinational Design: Implementation


Specification Versus Implementation


Two-Level Networks


Multilevel Networks


Multiplexers


Decoders


Memory


Programmable Logic Devices


Design Practices


Summary


Problems



Digital Engineering: Manufacturing Technologies



Logic Families


Electrical Signals and Logic Conventions


Metal-Oxide-Semiconductor Logic Families


Bipolar Logic Families


BiCMOS Logic Family


Electrical Characteristics


Summary


Problems



Integrated Circuits


Diode: The pn Junction


Metal-Oxide-Semiconductor Transistors


Bipolar Transistors


Fabrication and Packaging


Application-Specific Integrated Circuits (ASICs)


IC Economics


Summary


Problems



Digital Engineering: Sequential Systems



Sequential Systems: Definition And Analysis


Overview of Sequential Systems


Memory Devices


Literal Analysis


Symbolic Analysis


Timing Issues


Summary


Problems



Sequential Design: Synthesis


Simple Design Example


Generating State Diagrams from Prose


State Reduction


State Assignment and Encoded State Tables


Karnaugh Maps and Boolean Expressions


Exercise: Markov Speech Processor


Summary


Problems



Sequential Design: Implementation


Combinational Logic


Registers


Shift Registers


Counters


Sequential Programmable Logic Devices (PLDs)


Putting It All Together


Summary


Problems



VHDL: Combinational Systems



VHDL: A First look VHDL Presentation and Examples


Basic Language Organization


Interface


Architecture Body


Logic Operators


Concurrency


Design Units and Libraries


Summary


Problems



Structural Modeling In VHDL: Part I Example Schematic


Component and Signal Declarations


Component Instantiation Statements


Hierarchical Structures


Packages


Name Spaces and Scope


VHDL-93: Direct Design Entity Instantiation


Summary


Problems



Data Flow Modeling In VHDL Modeling Styles


Conditional Concurrent Signal Assignment Statement


Relational Operators


Selected Concurrent Signal Assignment Statement


Data Flow and Hardware Parallelism


Alternative Operators


Summary


Problems



Structural Modeling In VHDL: Part II Port Modes and Their Proper use


Constant-Valued and Unconnected Ports


Regular Structures


Generate Statements


Unconstrained Ports


Generics and Parameterized Design Entities


Arithmetic Operators


Integer and Floating Points Literals


VHDL-93: Foreign Architectures


VHDL-93: New Structure Attribute


Summary


Problems



Manufacturing Technologies



VHDL Technology Information: Part I Specifying Physical Values


Propagation Delay


Functions


VHDL-93: Pure and Impure Functions


Modeling Wired Logic


Prohibiting Wired Logic


Signals, Variables, and Constants


Summary


Problems



VHDL Technology Information: Part II Multi-Valued Logic


Enumeration Types


Arrays


VHDL-93: Bit String Literals


User-Defined At