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Advanced Digital Logic Design Using Verilog State Machines, and Synthesis for FPGAs

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ISBN-10: 0534551610

ISBN-13: 9780534551612

Edition: 2006

Authors: Sunggu Lee

List price: $219.95
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This textbook is intended to serve as a practical guide for the design of complex digital logic circuits such as digital control circuits, network interface circuits, pipelined arithmetic units, and RISC microprocessors. It is an advanced digital logic design textbook that emphasizes the use of synthesizable Verilog code and provides numerous fully worked-out practical design examples including a Universal Serial Bus interface, a pipelined multiply-accumulate unit, and a pipelined microprocessor for the ARM THUMB architecture.
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Book details

List price: $219.95
Copyright year: 2006
Publisher: Course Technology
Publication date: 3/16/2005
Binding: Hardcover
Pages: 462
Size: 7.25" wide x 9.25" long x 0.75" tall
Weight: 1.892
Language: English

Sunggu Lee received the B.S.E.E. degree with highest distinction from the University of Kansas, Lawrence, in 1985 and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1987 and 1990, respectively. He is currently an Associate Professor in the Department of Electronic and Electrical Engineering at the Pohang University of Science and Technology (POSTECH), Pohang, Korea. Prior to this appointment, he was an Assistant Professor in the Department of Electrical Engineering at the University of Delaware in Newark, Delaware, U.S.A. From June 1997 to June 1998, he spent one year as a Visiting Scientist at the IBM T. J. Watson Research Center. His research interests are in…    

Condensed Overview of Introductory Digital Logic Design
Number Formats
Combinational Logic
Combinational Logic Devices
Combinational Logic Circuit Design
Sequential Logic
Sequential Logic Devices
Synchronous Sequential Circuit Design
Hazards and Glitches
Digital Logic Design Using Hardware Description Languages
Hardware Description Languages
Design Flow
Register Transfer Level Notation
Logic Simulation
Properties of Actual Circuits
Introduction to Verilog and Test Benches
Verilog Basics
The Module Definition
Signals and Operators
Structural and Behavioral Descriptions
Testing and the Test Bench
Manufacturing Testing
Functional Testing
Test Benches
More Advanced Verilog Concepts
Concurrent and Sequential Verilog
Delay Modeling
Different Types of Assignment Statements
Parameters and Modeling a Bidirectional Bus
Tasks and Functions
Construction of Complete Verilog Programs
Combinational Logic Circuits
Sequential Logic Circuits
Behavioral Modeling of More Complex Circuits
High-Level Verilog Coding for Synthesis
Register Transfer Level Notation
Combinational Logic Synthesis
Using Continuous Assignment for Combinational Logic
Using Always Blocks for Combinational Logic
Complex Combinational Logic Example
Sequential Logic Synthesis
Synthesis Heuristics
Synthesis Using a Commercial Tool
High-Level Verilog Coding
State Machine Design
Manual State Machine Design
RTL Program
State Diagram
Control Logic
State Machine Design Using ASM Charts
Automatic Synthesis-Based State Machine Design
Automatic Synthesis-Based Design Procedure
Algorithm to HDL Code Conversion
Design Example: Vending Machine
Automatic State Machine Design for a Vending Machine
Manual State Machine Design for a Vending Machine
Timing Diagram
Correspondence Between Automatic and Manual Designs
Design Example: LCD Controller
Target LCD Module
Verilog Solution
FPGA and Other Programmable Logic Devices
Programmable Logic Devices
Circuit Customization
Programmable Logic Arrays
Programmable Read Only Memories
Programmable AND-Array Logic
Field Programmable Gate Arrays
Gate Arrays
FPGA Overview
Xilinx FPGA Example
FPGA Configuration
Xilinx Spartan-II FPGA Configuration Example
Boundary Scan
Design of a USB Protocol Analyzer
Overview of USB Full-Speed Mode
Packet Transfer Protocol
Initialization Sequence
Physical Layer Interface
USB Packets
Cyclic Redundancy Checks
Observation of Actual USB Signals
Design Overview
State Machine
Subcircuit Partitioning
Verilog Solution
Digital Phase Locked Loop
NRZI-to-Binary Converter
CRC Checker Submodules
Packet ID Recognizer
State Machine Subcircuit
Top-Level Module
Test Bench Code for Entire Circuit
Simulation Results
Design of Fast Arithmetic Units
Adder Designs
Ripple Carry adder
Carry Lookahead Adder
Carry Save Adder
Multiplier Designs
Combinational Multiplier
Sequential Multiplier
Fast Multiplication
Multiply-Accumulate Units
Pipelined Functional Units
Introduction to Pipelining
Pipelined Multiply-Accumulate Units
HDL Implementations
HDL Implementation Overview
HDL Design for a Pipelined Multiply-Accumulate Unit
Test Bench and Simulation Results
Design of a Pipelined RISC Microprocessor
Introduction to Microprocessors
Reduced Instruction Set Computers
Basic Computer Operation
The THUMB Micro