Low-Power CMOS VLSI Circuit Design

Name: Low-Power CMOS VLSI Circuit Design
Price: 26.79 USD
Availability: InStock
ISBN: 9780471114888

ISBN-10: 047111488X

ISBN-13: 9780471114888

Edition: 1999

Authors: Kaushik Roy, Sharat Prasad

List price: $197.95

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Description:

The solutions and reasoning behind circuit design based on the CMOS VLSI are presented in this book along with details on how to effectively cut power consumption. The book contains coverage of power management for MCMs, provides stochastic models detailing circuit activity, and includes chapter-ending exercises.

Book details

List price: $197.95
Copyright year: 1999
Publisher: John Wiley & Sons, Incorporated
Publication date: 2/22/2000
Binding: Hardcover
Pages: 376
Size: 6.44" wide x 9.72" long x 0.86" tall
Weight: 1.540

Peter Lorge is Senior Lecturer in Chinese History at Vanderbilt University, US.Kaushik Roy is Reader in the Department of History at Jadavpur University, India.



Preface



Low-Power Cmos Vlsi Design



Introduction



Sources of Power Dissipation



Designing for Low Power



Conclusions


References



Physics of Power Dissipation in Cmos Fet Devices



Introduction



Physics of Power Dissipation in MOSFET Devices



The MIS Structure



Long-Channel MOSFET



Submicron MOSFET



Gate-Induced Drain Leakage



Power Dissipation in CMOS



Short-Circuit Dissipation



Dynamic Dissipation



The Load Capacitance



Low-Power VLSI Design: Limits



Principles of Low-Power Design



Hierarchy of Limits



Fundamental Limits



Material Limits



Device Limits



Circuit Limits



System Limits



Practical Limits



Quasi-Adiabatic Microelectronics



Conclusions


References



Power Estimation



Modeling of Signals



Signal Probability Calculation



Signal Probability Using Binary Decision Diagrams



Probabilistic Techniques for Signal Activity Estimation



Switching Activity in Combinational Logic



Derivation of Activities for Static CMOS from Signal Probabilities



Switching Activity in Sequential Circuits



An Approximate Solution Method



Statistical Techniques



Estimating Average Power in Combinatorial Circuits



Estimating Average Power in Sequential Circuits



Estimation of Glitching Power



Monte-Carlo-Based Estimation of Glitching Power



Delay Models



Sensitivity Analysis



Power Sensitivity



Power Sensitivity Estimation



Power Sensitivity Method to Estimate Minimum and Maximum Average Power



Power Estimation Using Input Vector Compaction



Power Dissipation in Domino CMOS



Circuit Reliability



Power Estimation at the Circuit Level



Power Consumption of CMOS Gates



High-Level Power Estimation



Information-Theory-Based Approaches



Estimation of Maximum Power



Test-Generation-Based Approach



Approach Using the Steepest Descent



Genetic-Algorithm-Based Approach



Summary and Conclusion


References



Synthesis for Low Power



Behavioral Level Transforms



Algorithm Level Transforms for Low Power



Power-Constrained Least-Squares Optimization for Adaptive and Nonadaptive Filters



Circuit Activity Driven Architectural Transformations



Architecture-Driven Voltage Scaling



Power Optimization Using Operation Reduction



Power Optimization Using Operation Substitution



Precomputation-Based Optimization for Low Power



Logic Level Optimization for Low Power



FSM and Combinational Logic Synthesis



Technology Mapping



Circuit Level



Circuit Level Transforms



CMOS Gates



Transistor Sizing



Summary and Future Directions


References



Design and Test of Low-Voltage Cmos Circuits



Introduction



Circuit Design Style



Nonclocked Logic



Clocked Logic Family



Leakage Current in Deep Submicrometer Transistors



Transistor Leakage Mechanisms



Leakage Current Estimation



Deep Submicrometer Device Design Issues



Short-Channel Threshold Voltage Roll-Off



Drain-Induced Barrier Lowering



Key to Minimizing SCE



Low-Voltage Circuit Design Techniques



Reverse V[subscript gs]



Steeper Subthreshold Swing



Multiple Threshold Voltage



Multiple Threshold CMOS Based on Path Criticality



Testing Deep Submicrometer ICs with Elevated Intrinsic Leakage



Multiple Supply Voltages



Conclusions


References



Low-Power Static Ram Architectures



Introduction



Organization of a Static RAM



MOS Static RAM Memory Cell



The 4T SRAM Cell



The 6T SRAM Cell



SRAM Cell Operation



Banked Organization of SRAMs



Divided Word Line Architecture



Reducing Voltage Swings on Bit Lines



Pulsed Word Lines



Self-Timing the RAM Core



Precharge Voltage for Bit Lines



Reducing Power in the Write Driver Circuits



Reducing Power in Sense Amplifier Circuits



Method for Achieving Low Core Voltages from a Single Supply



Summary


References



Low-Energy Computing Using Energy Recovery Techniques



Energy Dissipation in Transistor Channel Using an RC Model



Energy Recovery Circuit Design



Designs with Partially Reversible Logic



Designs with Reversible Logic



Simple Charge Recovery Logic Modified from Static CMOS Circuits



Adiabatic Dynamic Logic



Energy Recovery SRAM Core



Another Core Organization: Column-Activated Memory Core



Energy Dissipation in Memory Core



Comparison of Two Memory Core Organizations



Design of Peripheral Circuits



Optimal Voltage Selection



Supply Clock Generation



Summary and Conclusions


References



Software Design for Low Power



Introduction



Sources of Software Power Dissipation



Software Power Estimation



Gate Level Power Estimation



Architecture Level Power Estimation



Bus Switching Activity



Instruction Level Power Analysis



Software Power Optimizations



Algorithm Transformations to Match Computational Resources



Minimizing Memory Access Costs



Instruction Selection and Ordering



Power Management



Automated Low-Power Code Generation



Codesign for Low Power



Instruction Set Design



Reconfigurable Computing



Architecture and Circuit Level Decisions



Summary


References


Index