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Preface | |
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Low-Power Cmos Vlsi Design | |
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Introduction | |
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Sources of Power Dissipation | |
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Designing for Low Power | |
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Conclusions | |
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References | |
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Physics of Power Dissipation in Cmos Fet Devices | |
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Introduction | |
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Physics of Power Dissipation in MOSFET Devices | |
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The MIS Structure | |
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Long-Channel MOSFET | |
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Submicron MOSFET | |
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Gate-Induced Drain Leakage | |
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Power Dissipation in CMOS | |
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Short-Circuit Dissipation | |
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Dynamic Dissipation | |
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The Load Capacitance | |
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Low-Power VLSI Design: Limits | |
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Principles of Low-Power Design | |
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Hierarchy of Limits | |
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Fundamental Limits | |
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Material Limits | |
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Device Limits | |
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Circuit Limits | |
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System Limits | |
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Practical Limits | |
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Quasi-Adiabatic Microelectronics | |
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Conclusions | |
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References | |
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Power Estimation | |
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Modeling of Signals | |
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Signal Probability Calculation | |
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Signal Probability Using Binary Decision Diagrams | |
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Probabilistic Techniques for Signal Activity Estimation | |
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Switching Activity in Combinational Logic | |
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Derivation of Activities for Static CMOS from Signal Probabilities | |
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Switching Activity in Sequential Circuits | |
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An Approximate Solution Method | |
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Statistical Techniques | |
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Estimating Average Power in Combinatorial Circuits | |
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Estimating Average Power in Sequential Circuits | |
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Estimation of Glitching Power | |
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Monte-Carlo-Based Estimation of Glitching Power | |
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Delay Models | |
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Sensitivity Analysis | |
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Power Sensitivity | |
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Power Sensitivity Estimation | |
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Power Sensitivity Method to Estimate Minimum and Maximum Average Power | |
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Power Estimation Using Input Vector Compaction | |
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Power Dissipation in Domino CMOS | |
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Circuit Reliability | |
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Power Estimation at the Circuit Level | |
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Power Consumption of CMOS Gates | |
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High-Level Power Estimation | |
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Information-Theory-Based Approaches | |
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Estimation of Maximum Power | |
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Test-Generation-Based Approach | |
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Approach Using the Steepest Descent | |
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Genetic-Algorithm-Based Approach | |
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Summary and Conclusion | |
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References | |
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Synthesis for Low Power | |
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Behavioral Level Transforms | |
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Algorithm Level Transforms for Low Power | |
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Power-Constrained Least-Squares Optimization for Adaptive and Nonadaptive Filters | |
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Circuit Activity Driven Architectural Transformations | |
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Architecture-Driven Voltage Scaling | |
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Power Optimization Using Operation Reduction | |
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Power Optimization Using Operation Substitution | |
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Precomputation-Based Optimization for Low Power | |
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Logic Level Optimization for Low Power | |
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FSM and Combinational Logic Synthesis | |
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Technology Mapping | |
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Circuit Level | |
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Circuit Level Transforms | |
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CMOS Gates | |
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Transistor Sizing | |
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Summary and Future Directions | |
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References | |
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Design and Test of Low-Voltage Cmos Circuits | |
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Introduction | |
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Circuit Design Style | |
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Nonclocked Logic | |
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Clocked Logic Family | |
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Leakage Current in Deep Submicrometer Transistors | |
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Transistor Leakage Mechanisms | |
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Leakage Current Estimation | |
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Deep Submicrometer Device Design Issues | |
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Short-Channel Threshold Voltage Roll-Off | |
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Drain-Induced Barrier Lowering | |
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Key to Minimizing SCE | |
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Low-Voltage Circuit Design Techniques | |
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Reverse V[subscript gs] | |
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Steeper Subthreshold Swing | |
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Multiple Threshold Voltage | |
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Multiple Threshold CMOS Based on Path Criticality | |
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Testing Deep Submicrometer ICs with Elevated Intrinsic Leakage | |
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Multiple Supply Voltages | |
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Conclusions | |
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References | |
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Low-Power Static Ram Architectures | |
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Introduction | |
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Organization of a Static RAM | |
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MOS Static RAM Memory Cell | |
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The 4T SRAM Cell | |
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The 6T SRAM Cell | |
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SRAM Cell Operation | |
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Banked Organization of SRAMs | |
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Divided Word Line Architecture | |
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Reducing Voltage Swings on Bit Lines | |
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Pulsed Word Lines | |
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Self-Timing the RAM Core | |
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Precharge Voltage for Bit Lines | |
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Reducing Power in the Write Driver Circuits | |
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Reducing Power in Sense Amplifier Circuits | |
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Method for Achieving Low Core Voltages from a Single Supply | |
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Summary | |
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References | |
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Low-Energy Computing Using Energy Recovery Techniques | |
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Energy Dissipation in Transistor Channel Using an RC Model | |
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Energy Recovery Circuit Design | |
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Designs with Partially Reversible Logic | |
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Designs with Reversible Logic | |
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Simple Charge Recovery Logic Modified from Static CMOS Circuits | |
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Adiabatic Dynamic Logic | |
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Energy Recovery SRAM Core | |
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Another Core Organization: Column-Activated Memory Core | |
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Energy Dissipation in Memory Core | |
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Comparison of Two Memory Core Organizations | |
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Design of Peripheral Circuits | |
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Optimal Voltage Selection | |
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Supply Clock Generation | |
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Summary and Conclusions | |
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References | |
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Software Design for Low Power | |
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Introduction | |
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Sources of Software Power Dissipation | |
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Software Power Estimation | |
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Gate Level Power Estimation | |
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Architecture Level Power Estimation | |
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Bus Switching Activity | |
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Instruction Level Power Analysis | |
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Software Power Optimizations | |
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Algorithm Transformations to Match Computational Resources | |
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Minimizing Memory Access Costs | |
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Instruction Selection and Ordering | |
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Power Management | |
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Automated Low-Power Code Generation | |
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Codesign for Low Power | |
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Instruction Set Design | |
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Reconfigurable Computing | |
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Architecture and Circuit Level Decisions | |
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Summary | |
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References | |
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Index | |