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Preface | |
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Acknowledgments | |
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Basic Digital Circuits | |
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Gate-level combinational circuit | |
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Introduction | |
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General description | |
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Basic lexical elements and data types | |
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Data types | |
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Program skeleton | |
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Structural description | |
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Testbench | |
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Bibliographic notes | |
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Suggested experiments | |
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Overview of FPGA and EDA software | |
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Introduction | |
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FPGA | |
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Overview of the Digilent S3 board | |
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Development flow | |
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Overview of the Xilinx ISE project navigator | |
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Short tutorial on ISE project navigator | |
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Short tutorial on the ModelSim HDL simulator | |
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Bibliographic notes | |
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Suggested experiments | |
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RT-level combinational circuit | |
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Introduction | |
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Operators | |
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Always block for a combinational circuit | |
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If statement | |
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Case statement | |
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Routing structure of conditional control constructs | |
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General coding guidelines for an always block | |
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Parameter and constant | |
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Design examples | |
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Bibliographic notes | |
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Suggested experiments | |
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Regular Sequential Circuit | |
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Introduction | |
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HDL code of the FF and register | |
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Simple design examples | |
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Testbench for sequential circuits | |
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Case study | |
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Bibliographic notes | |
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Suggested experiments | |
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FSM | |
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Introduction | |
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FSM code development | |
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Design examples | |
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Bibliographic notes | |
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Suggested experiments | |
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FSMD | |
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Introduction | |
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Code development of an FSMD | |
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Design examples | |
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Bibliographic notes | |
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Suggested experiments | |
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Selected Topics of Verilog | |
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Blocking versus nonblocking assignment | |
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Alternative coding style for sequential circuit | |
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Use of the signed data type | |
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Use of function in synthesis | |
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Additional constructs for testbench development | |
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Bibliographic notes | |
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Suggested experiments | |
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I/O Modules | |
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UART | |
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Introduction | |
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UART receiving subsystem | |
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UART transmitting subsystem | |
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Overall UART system | |
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Customizing a UART | |
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Bibliographic notes | |
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Suggested experiments | |
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PS2 Keyboard | |
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Introduction | |
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PS2 receiving subsystem | |
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PS2 keyboard scan code | |
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PS2 keyboard interface circuit | |
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Bibliographic notes | |
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Suggested experiments | |
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PS2 Mouse | |
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Introduction | |
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PS2 mouse protocol | |
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PS2 transmitting subsystem | |
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Bidirectional PS2 interface | |
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PS2 mouse interface | |
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Bibliographic notes | |
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Suggested experiments | |
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External SRAM | |
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Introduction | |
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Specification of the IS61LV25616AL SRAM | |
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Basic memory controller | |
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A safe design | |
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More aggressive design | |
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Bibliographic notes | |
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Suggested experiments | |
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Xilinx Spartan-3 Specific Memory | |
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Introduction | |
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Embedded memory of Spartan-3 device | |
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Method to incorporate memory modules | |
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HDL templates for memory inference | |
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Bibliographic notes | |
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Suggested experiments | |
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VGA controller I: graphic | |
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Introduction | |
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VGA synchronization | |
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Overview of the pixel generation circuit | |
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Graphic generation with an object-mapped scheme | |
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Graphic generation with a bit-mapped scheme | |
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Bibliographic notes | |
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Suggested experiments | |
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VGA controller II: text | |
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Introduction | |
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Text generation | |
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Full-screen text display | |
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The complete pong game | |
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Bibliographic notes | |
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Suggested experiments | |
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Picoblaze Microcontroller[superscript XILINX SPECIFIC] | |
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PicoBlaze Overview | |
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Introduction | |
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Customized hardware and customized software | |
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Overview of PicoBlaze | |
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Development flow | |
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Instruction set | |
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Assembler directives | |
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Bibliographic notes | |
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PicoBlaze Assembly Code Development | |
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Introduction | |
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Useful code segments | |
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Subroutine development | |
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Program development | |
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Processing of the assembly code | |
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Syntheses with PicoBlaze | |
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Bibliographic notes | |
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Suggested experiments | |
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PicoBlaze I/O Interface | |
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Introduction | |
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Output port | |
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Input port | |
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Square program with a switch and seven-segment LED display interface | |
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Square program with a combinational multiplier and UART console | |
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Bibliographic notes | |
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Suggested experiments | |
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PicoBlaze Interrupt Interface | |
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Introduction | |
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Interrupt handling in PicoBlaze | |
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External interface | |
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Software development considerations | |
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Design example | |
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Bibliographic notes | |
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Suggested experiments | |
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Sample Verilog templates | |
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Numbers and operators | |
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Sized and unsized numbers | |
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Operators | |
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General Verilog constructs | |
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Overall code structure | |
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Component instantiation | |
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Routing with conditional operator and if and case statements | |
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Conditional operator and if statement | |
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Case statement | |
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Combinational circuit using an always block | |
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Always block without default output assignment | |
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Always block with default output assignment | |
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Memory Components | |
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Register template | |
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Register file | |
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Regular sequential circuits | |
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FSM | |
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FSMD | |
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S3 board constraint file (s3. ucf) | |
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References | |
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Topic Index | |