Rapid Prototyping of Digital Systems

Name: Rapid Prototyping of Digital Systems
Price: 23.15 USD
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ISBN: 9780387726700

ISBN-10: 0387726705

ISBN-13: 9780387726700

Edition: 2nd 2008

Authors: James O. Hamblen, Tyson S. Hall, Michael D. Furman

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New to this edition is an introduction to embedded operating systems for SOPC designs. The ?Clinux OS is configured for Altera's DE1 and DE2 boards and is provided on a DVD along with several application programs. Featuring four accelerated tutorials on the Quartus II and Nios II design environments, this edition progresses from introductory programmable logic to full-scale SOPC design integrating hardware implementation, software development, operating system support, state-of-the-art I/O, and IP cores. This edition features Altera's new 7.1 Quartus II CAD and Nios II SOPC tools and includes projects for Altera's DE1, DE2, UP3, UP2, and UP1 FPGA development boards. Laboratory projects…

Book details

List price: $74.95
Edition: 2nd
Copyright year: 2008
Publisher: Springer
Publication date: 11/9/2007
Binding: Mixed Media
Pages: 411
Size: 6.75" wide x 10.00" long x 1.00" tall
Weight: 2.288
Language: English




Tutorial I: The 15 Minute Design



Design Entry using the Graphic Editor



Compiling the Design



Simulation of the Design



Testing Your Design on an FPGA Board



Downloading Your Design to the DE1 Board



Downloading Your Design to the DE2 Board



Downloading Your Design to the UP3 Board



Downloading Your Design to the UP2 or UP1 Board



The 10 Minute VHDL Entry Tutorial



Compiling the VHDL Design



The 10 Minute Verilog Entry Tutorial



Compiling the Verilog Design



Timing Analysis



The Floorplan Editor



Symbols and Hierarchy



Functional Simulation



Laboratory Exercises






FPGA and External Hardware Features



The FPGA Board's Memory Features



The FPGA Board's I/O Features



Obtaining an FPGA Development Board and Cables



Programmable Logic Technology



CPLDs and FPGAs



Altera MAX 7000S Architecture - A Product Term CPLD Device



Altera Cyclone Architecture - A Look-Up Table FPGA Device



Xilinx 4000 Architecture - A Look-Up Table FPGA Device



Computer Aided Design Tools for Programmable Logic



Next Generation FPGA CAD tools



Applications of FPGAs



Features of New Generation FPGAs



For additional information



Laboratory Exercises



Tutorial II: Sequential Design and Hierarchy



Install the Tutorial Files and FPGAcore Library for your board



Open the tutor2 Schematic



Browse the Hierarchy



Using Buses in a Schematic



Testing the Pushbutton Counter and Displays



Testing the Initial Design on the Board



Fixing the Switch Contact Bounce Problem



Testing the Modified Design on the FPGA Board



Laboratory Exercises



FPGAcore Library Functions



FPGAcore LCD_Display: LCD Panel Character Display



FPGAcore DEC_7SEG: Hex to Seven-segment Decoder



FPGAcore Debounce: Pushbutton Debounce



FPGAcore OnePulse: Pushbutton Single Pulse



FPGAcore Clk_Div: Clock Divider



FPGAcore VGA_Sync: VGA Video Sync Generation



FPGAcore Char_ROM: Character Generation ROM



FPGAcore Keyboard: Read Keyboard Scan Code



FPGAcore Mouse: Mouse Cursor



For additional information



Using VHDL for Synthesis of Digital Hardware



VHDL Data Types



VHDL Operators



VHDL Based Synthesis of Digital Hardware



VHDL Synthesis Models of Gate Networks



VHDL Synthesis Model of a Seven-segment LED Decoder



VHDL Synthesis Model of a Multiplexer



VHDL Synthesis Model of Tri-State Output



VHDL Synthesis Models of Flip-flops and Registers



Accidental Synthesis of Inferred Latches



VHDL Synthesis Model of a Counter



VHDL Synthesis Model of a State Machine



VHDL Synthesis Model of an ALU with an Adder/Subtractor and a Shifter



VHDL Synthesis of Multiply and Divide Hardware



VHDL Synthesis Models for Memory



Hierarchy in VHDL Synthesis Models



Using a Testbench for Verification



For additional information



Laboratory Exercises



Using Verilog for Synthesis of Digital Hardware



Verilog Data Types



Verilog Based Synthesis of Digital Hardware



Verilog Operators



Verilog Synthesis Models of Gate Networks



Verilog Synthesis Model of a Seven-segment LED Decoder



Verilog Synthesis Model of a Multiplexer



Verilog Synthesis Model of Tri-State Output



Verilog Synthesis Models of Flip-flops and Registers



Accidental Synthesis of Inferred Latches



Verilog Synthesis Model of a Counter



Verilog Synthesis Model of a State Machine



Verilog Synthesis Model of an ALU with an Adder/Subtractor and a Shifter



Verilog Synthesis of Multiply and Divide Hardware



Verilog Synthesis Models for Memory



Hierarchy in Verilog Synthesis Models



For additional information



Laboratory Exercises



State Machine Design: The Electric Train Controller



The Train Control Problem



Train Direction Outputs (DA1-DA0, and DB1-DB0)



Switch Direction Outputs (SW1, SW2, and SW3)



Train Sensor Input Signals (S1, S2, S3, S4, and S5)



An Example Controller Design



VHDL Based Example Controller Design



Verilog Based Example Controller Design



Automatically Generating a State Diagram of a Design



Simulation Vector file for State Machine Simulation



Running the Train Control Simulation



Running the Video Train System (After Successful Simulation)



A Hardware Implementation of the Train System Layout



Laboratory Exercises



A Simple Computer Design: The ï¿½P 3



Computer Programs and Instructions



The Processor Fetch, Decode and Execute Cycle



VHDL Model of the ï¿½P 3



Verilog Model of the ï¿½P 3



Automatically Generating a State Diagram of the ï¿½P3



Simulation of the ï¿½P3 Computer



Laboratory Exercises






Video Display Technology



Video Refresh



Using an FPGA for VGA Video Signal Generation



A VHDL Sync Generation Example: FPGAcore VGA_SYNC



Final Output Register for Video Signals



Required Pin Assignments for Video Output



Video Examples



A Character Based Video Design



Character Selection and Fonts



VHDL Character Display Design Examples



A Graphics Memory Design Example



Video Data Compression



Video Color Mixing using Dithering



VHDL Graphics Display Design Example



Higher Video Resolution and Faster Refresh Rates



Laboratory Exercises



Interfacing to the PS/2 Keyboard and Mouse



PS/2 Port Connections



Keyboard Scan Codes



Make and Break Codes



The PS/2 Serial Data Transmission Protocol



Scan Code Set 2 for the PS/2 Keyboard



The Keyboard FPGAcore



A Design Example Using the Keyboard FPGAcore



Interfacing to the PS/2 Mouse



The Mouse FPGAcore



Mouse Initialization



Mouse Data Packet Processing



An Example Design Using the Mouse FPGAcore



For Additional Information



Laboratory Exercises



Legacy Digital I/O Interfacing Standards



Parallel I/O Interface



RS-232C Serial I/O Interface



SPI Bus Interface



I<sup>2</sup>C Bus Interface



For Additional Information



Laboratory Exercises



FPGA Robotics Projects



The FPGA-bot Design



FPGA-bot Servo Drive Motors



Modifying the Servos to make Drive Motors



VHDL Servo Driver Code for the FPGA-bot



Low-cost Sensors for an FPGA Robot Project



Assembly of the FPGA-bot Body



I/O Connections to the board's Expansion Headers



Robot Projects Based on R/C Toys, Models, and Robot Kits



For Additional Information



Laboratory Exercises






The MIPS Instruction Set and Processor



Using VHDL to Synthesize the MIPS Processor Core



The Top-Level Module



The Control Unit



The Instruction Fetch Stage



The Decode Stage



The Execute Stage



The Data Memory Stage



Simulation of the MIPS Design



MIPS Hardware Implementation on the FPGA Board



For Additional Information



Laboratory Exercises



Introducing System-on-a-Programmable-Chip



Processor Cores



SOPC Design Flow



Initializing Memory



SOPC Design versus Traditional Design Modalities



An Example SOPC Design



Hardware/Software Design Alternatives



For additional information



Laboratory Exercises



Tutorial III: Nios II Processor Software Development



Install the DE board files



Starting a Nios II Software Project



The Nios II IDE Software



Generating the Nios II System Library



Software Design with Nios II Peripherals



Starting Software Design - main()



Downloading the Nios II Hardware and Software Projects



Executing the Software



Starting Software Design for a Peripheral Test Program



Handling Interrupts



Accessing Parallel I/O Peripherals



Communicating with the LCD Display (DE2 only)



Testing SRAM



Testing Flash Memory



Testing SDRAM



Downloading the Nios II Hardware and Software Projects



Executing the Software



For additional information



Laboratory Exercises



Tutorial IV: Nios II Processor Hardware Design



Install the DE board files



Creating a New Project



Starting SOPC Builder



Adding a Nios II Processor



Adding UART Peripherals



Adding an Interval Timer Peripheral



Adding Parallel I/O Components



Adding an SRAM Memory Controller



Adding an SDRAM Memory Controller



Adding the LCD Module (DE2 Board Only)



Adding an External Bus



Adding Components to the External Bus



Global Processor Settings



Finalizing the Nios II Processor



Add the Processor Symbol to the Top-Level Schematic



Create a Phase-Locked Loop Component



Complete the Top-Level Schematic



Design Compilation



Testing the Nios II Project



For additional information



Laboratory Exercises



Operating System Support for SOPC Design



Nios II OS Support



eCos



ï¿½C/OS-II



ï¿½Clinux



Implementing the ï¿½Clinux on the DE Board



Hardware Design for ï¿½Clinux Support



Configuring the DE Board



Exploring ï¿½Clinux on the DE Board



PS/2 Device Support in ï¿½Clinux



Video Display in ï¿½Clinux



USB Devices in ï¿½Clinux (DE2 Board Only)



Network Communication in ï¿½Clinux (DE2 Board Only)



For additional information



Laboratory Exercises



Generation of Pseudo Random Binary Sequences



Quartus II Design and Data File Extensions



Common FPGA Pin Assignments



ASCII Character Code



Common I/O Connector Pin Assignments


Glossary


Index


About the Accompanying DVD