Digital VLSI Chip Design with Cadence and Synopsys CAD Tools

ISBN-10: 0321547993

ISBN-13: 9780321547996

Edition: 2010

Authors: Erik Brunvand

List price: $48.40
30 day, 100% satisfaction guarantee

If an item you ordered from TextbookRush does not meet your expectations due to an error on our part, simply fill out a return request and then return it by mail within 30 days of ordering it for a full refund of item cost.

Learn more about our returns policy


what's this?
Rush Rewards U
Members Receive:
You have reached 400 XP and carrot coins. That is the daily max!
Study Briefs

Limited time offer: Get the first one free! (?)

All the information you need in one place! Each Study Brief is a summary of one specific subject; facts, figures, and explanations to help you learn faster.

Add to cart
Study Briefs
SQL Online content $4.95 $1.99
Add to cart
Study Briefs
MS Excel® 2010 Online content $4.95 $1.99
Add to cart
Study Briefs
MS Word® 2010 Online content $4.95 $1.99
Add to cart
Study Briefs
MS PowerPoint® 2010 Online content $4.95 $1.99
Customers also bought

Book details

List price: $48.40
Copyright year: 2010
Publisher: Addison Wesley
Publication date: 2/25/2009
Binding: Paperback
Pages: 624
Size: 7.00" wide x 8.75" long x 1.00" tall
Weight: 1.892

CAD Tool Flows
Custom VLSI and Cell Design Flow
Hierarchical Cell/Block ASIC Flow
What This Book Is and Isn't
Bugs in the Tools?
Tool Setup and Execution Scripts
Typographical Conventions
Cadence DFII and ICFB
Cadence Design Framework
Starting Cadence
Composer Schematic Capture
Starting Cadence and Making a New Working Library
Creating a New Cell
Creating the Schematic View of a Full Adder
Creating the Symbol View of a Full Adder
Creating a Two-Bit Adder Using the FullAdder Bit
Schematics that Use Transistors
Printing Schematics
Modifying PostScript Plot Files
Variable, Pin, and Cell Naming Restrictions
Verilog Simulation
Verilog Simulation of Composer Schematics
Verilog-XL: Simulating a Schematic
NC Verilog: Simulating a Schematic
Behavioral Verilog Code in Composer
Generating a Behavioral View
Simulating a Behavioral View
Stand-Alone Verilog Simulation
NC Verilog
Timing in Verilog Simulations
Behavioral Versus Transistor Switch Simulation
Behavioral Gate Timing
Standard Delay Format (SDF) Timing
Transistor Timing
Virtuoso Layout Editor
An Inverter Schematic
Starting Cadence icfb
Making an Inverter Schematic
Making an Inverter Symbol
Layout for an Inverter
Creating a New layout View
Drawing an nmos Transistor
Drawing a pmos Transistor
Assembling the Inverter from the Transistor Layouts
Using Hierarchy in Layout
Virtuoso Command Overview
Printing Layouts
Design Rule Checking
DIVA Design Rule Checking
Generating an Extracted View
Layout Versus Schematic Checking (LVS)
Generating an analog-extracted View
Overall Cell Design Flow (So Far.)
Standard Cell Design Template
Standard Cell Geometry Specification
Standard Cell I/O Pin Placement
Standard Cell Transistor Sizing
Spectre Analog Simulator
Simulating a Schematic (Transient Simulation)
Simulation with the Spectre Analog Environment
Simulating with a Config View
Mixed Analog/Digital Simulation
Final Words about Mixed-Mode Simulation
DC Simulation
Parametric Simulation
Power Measurements
Cell Characterization
Liberty File Format
Combinational Cell Definition
Sequential Cell Definition
Tristate Cell Definition
Cell Characterization with ELC
Generating the ELC Netlist
Cell Naming and Encounter Library Characterizer
Best, Typical, and Worst Case Characterization
Cell Characterization with Spectre
Converting Liberty to Synopsys Database (db) Format
Verilog Synthesis
Synopsys Design Compiler Synthesis with dc shell
Basic Synthesis
Scripted Synthesis
Synopsys Design Vision GUI
DesignWare Building Blocks
Cadence RTL Compiler Synthesis
Scripted Synthesis
Cadence RTL Compiler GUI
Importing Structural Verilog into Cadence DFII
Post-Synthesis Verilog Simulation
Abstract Generation
Reading Your Library into Abstract
Finding Pins in Your Cells
The Extract Step
The Abstract Step
LEF File Generation
Modifying the LEF File
SOC Encounter Place and Route
Encounter GUI
Reading In the Design
Power Planning
Placing the Standard Cells
First Optimization Phase
Clock Tree Synthesis
Post-CTS Optimization
Final Routing
Post-Route Optimization
Adding Filler Cells
Checking the Result
Saving and Exporting the Placed and Routed Cell
Reading the Cell Back into Virtuoso
Design Import with Configuration Files
SOC Encounter Scripting
Chip Assembly
Module Routing with ccar
Preparing a Placement with Virtuoso-XL
Invoking the ccar Router
Core to Pad Frame Routing with ccar
Copy the Pad Frame
Modify the Frame schematic View
Modify the Frame layout View
Routing the Core to Frame with ccar
Metal Density Issues
Final GDSII Generation
Design Example
Tiny MIPS: Flat Tool Flow
Place and Route
Final Assembly
Tiny MIPS: Hierarchical Tool Flow
Place and Route into a Macro Block
Preparing Custom Circuits for Hierarchy
Generating Abstract Views for Blocks
Place and Route with Macro Blocks
Final Assembly
Tool and Setup Scripts
Cadence Tool Installation
Cadence Setup Scripts
setup-cadence: Basic Cadence Setup
setup-ncsu: Cadence Setup with NCSU Extensions
Shell Scripts for Cadence Tools
syn-abstract: Start the Abstract Tool
cad-alf2lib: Convert the alf Notation from Encounter Library Characterizer to lib Notation
cad-elc: Start the Encounter Library Characterizer
cad-ncsu: Start the DFII (icfb) Environment
cad-soc: Start the SOC Encounter Place and Route Tool
sim-ncg: Startup Script for the NC Verilog Simulator, with GUI
sim-xlg: Startup Script for the Verilog-XL simulator, with GUI
sptr2elc: Perl Script for Converting Spectre Netlists to Encounter Library Characterizer Netlists
syn-rtlg: Start the RTL Compiler Synthesis Tool, with GUI
Synopsys Tool Installation
Synopsys Setup Scripts
setup-synopsys: Basic Synopsys Setup
Shell Scripts for Synopsys Tools
sim-vcs: Startup Script for the VCS Verilog Simulator
sim-simv: Startup Script for the simv Simulator Resulting from VCS Execution
syn-dc: Startup Script for Design Compiler Synthesis
syn-dv: Startup Script for Design Compiler using the Design Vision GUI
Scripts to Drive the Tools
Tcl Script Basics
Cadence Tool Scripts
Encounter Library Characterizer Cell Characterization
Cell Characterization with Spectre
SOC Encounter Place and Route
RTL Compiler Synthesis
ccar Chip Assembly Tool
Synopsys Tool Scripts
Synopsys Design Compiler Script Files
Technology and Cell Libraries
NCSU Cadence Design Kit CDK1.5 Installation
cdsinit: Local Modifications
cdsenv: Local Modifications
UofU TechLib ami06: Local Modifications
Example Standard Cells
Example Liberty File
LEF File Technology Header
LEF File MACRO Examples
Free shipping on orders over $35*

*A minimum purchase of $35 is required. Shipping is provided via FedEx SmartPost® and FedEx Express Saver®. Average delivery time is 1 – 5 business days, but is not guaranteed in that timeframe. Also allow 1 - 2 days for processing. Free shipping is eligible only in the continental United States and excludes Hawaii, Alaska and Puerto Rico. FedEx service marks used by permission."Marketplace" orders are not eligible for free or discounted shipping.

Learn more about the TextbookRush Marketplace.