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Preface | |
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Digital Logic and Finite State Machines | |
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Digital Logic Fundamentals | |
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Boolean Algebra | |
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Basic Functions | |
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Manipulating Boolean Functions | |
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Basic Combinatorial Logic | |
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More Complex Combinatorial Components | |
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Multiplexers | |
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Decoders | |
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Encoders | |
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Comparators | |
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Adders and Subtracters | |
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Memory | |
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Combinatorial Circuit Designs | |
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BCD to 7-segment Decoder | |
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Data Sorter | |
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Practical Perspective: Why LED's Are Usually Active Low | |
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Basic Sequential Components | |
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More Complex Sequential Components | |
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Counters | |
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Shift Registers | |
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Real World Example: Programmable Logic Devices | |
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Historical Perspective: Digital Circuit Implementation | |
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Summary | |
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Problems | |
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Introduction to Finite State Machines | |
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State Diagrams and State Tables | |
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Historical Perspective: Finite State Machine and Microprocessors | |
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Mealy and Moore Machines | |
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Designing State Diagrams | |
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Modulo 6 Counter | |
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String Checker | |
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Toll Booth Controller | |
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Practical Perspective: Different Models For The Same Problem | |
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From State Diagram to Implementation | |
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Assigning State Values | |
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Mealy and Moore Machine Implementations | |
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Generating the Next State | |
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Generating System Outputs | |
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An Alternative Design | |
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The Eight-State String Checker | |
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Real World Example: Practical Considerations | |
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Unused States | |
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Asynchronous Designs | |
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Machine Conversion | |
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Summary | |
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Problems | |
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Computer Organization and Architecture | |
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Instruction Set Architectures | |
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Levels of Programming Languages | |
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Language Categories | |
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Compiling and Assembling Programs | |
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Practical Perspective: Java Applets--A Different Way of Processing Programs | |
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Assembly Language Instructions | |
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Instruction Types | |
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Data Types | |
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Addressing Modes | |
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Instruction Formats | |
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Instruction Set Architecture Design | |
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A Relatively Simple Instruction Set Architecture | |
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Real World Example: The 8085 Microprocessor Instruction Set Architecture | |
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The 8085 Microprocessor Register Set | |
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Historical Perspective: Intel's Early Microprocessors | |
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The 8085 Microprocessor Instruction Set | |
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A Simple 8085 Program | |
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Analyzing the 8085 Instruction Set Architecture | |
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Summary | |
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Problems | |
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Introduction to Computer Organization | |
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Basic Computer Organization | |
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System Buses | |
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Instruction Cycles | |
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Practical Perspective: The Peripheral Component Interconnect Bus | |
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CPU Organization | |
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Memory Subsystem Organization and Interfacing | |
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Types of Memory | |
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Internal Chip Organization | |
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Memory Subsystem Configuration | |
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Historical Perspective: The von Neumann and Harvard Architectures | |
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Multibyte Data Organization | |
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Beyond the Basics | |
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I/O Subsystem Organization and Interfacing | |
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A Relatively Simple Computer | |
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Real World Example: An 8085-based Computer | |
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Historical Perspective: The Sojourner Rover | |
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Summary | |
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Problems | |
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Register Transfer Languages | |
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Micro-Operations and Register Transfer Language | |
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Using RTL to Specify Digital Systems | |
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Specification of Digital Components | |
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Specification and Implementation of Simple Systems | |
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More Complex Digital Systems and RTL | |
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Modulo 6 Counter | |
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Toll Booth Controller | |
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Real World Example: VHDL-VHSIC Hardware Description Language | |
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Practical Perspective: Hardware Description Languages | |
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VHDL Syntax | |
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VHDL Design with a High Level of Abstraction | |
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VHDL Design with a Low Level of Abstraction | |
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Summary | |
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Practical Perspective: Some Advanced Capabilities of VHDL | |
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Problems | |
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CPU Design | |
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Specifying a CPU | |
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Design and Implementation of a Very Simple CPU | |
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Specifications for a Very Simple CPU | |
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Fetching Instructions from Memory | |
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Practical Perspective: Why a CPU Increments PC During the Fetch Cycle | |
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Decoding Instructions | |
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Executing Instructions | |
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Establishing Required Data Paths | |
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Design of a Very Simple ALU | |
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Designing the Control Unit Using Hardwired Control | |
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Design Verification | |
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Design and Implementation of a Relatively Simple CPU | |
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Specifications for a Relatively Simple CPU | |
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Fetching and Decoding Instructions | |
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Executing Instructions | |
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Establishing Data Paths | |
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Design of a Relatively Simple ALU | |
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Designing the Control Unit Using Hardwired Control | |
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Design Verification | |
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Shortcomings of the Simple CPUs | |
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More Internal Registers and Cache | |
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Historical Perspective: Storage in Intel Microprocessors | |
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Multiple Buses Within the CPU | |
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Pipelined Instruction Processing | |
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Larger Instruction Sets | |
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Subroutines and Interrupts | |
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Real World Example: Internal Architecture of the 8085 Microprocessor | |
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Summary | |
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Problems | |
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Microsequencer Control Unit Design | |
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Basic Microsequencer Design | |
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Microsequencer Operations | |
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Microinstruction Formats | |
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Design and Implementation of a Very Simple Microsequencer | |
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The Basic Layout | |
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Generating the Correct Sequence and Designing the Mapping Logic | |
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Generating the Micro-Operations Using Horizontal Microcode | |
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Generating the Micro-Operations Using Vertical Microcode | |
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Practical Perspective: Nanoinstructions | |
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Directly Generating the Control Signals from the Microcode | |
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Design and Implementation of a Relatively Simple Microsequencer | |
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Modifying the State Diagram | |
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Designing the Sequencing Hardware and Microcode | |
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Completing the Design Using Horizontal Microcode | |
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Reducing the Number of Microinstructions | |
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Microsubroutines | |
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Microcode Jumps | |
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Microprogrammed Control vs. Hardwired Control | |
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Complexity of the Instruction Set | |
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Ease of Modification | |
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Clock Speed | |
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Real World Example: A (Mostly) Microcoded CPU: The Pentium Processor | |
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Historical Perspective: How the Pentium Got Its Name | |
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Summary | |
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Problems | |
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Computer Arithmetic | |
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Unsigned Notation | |
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Addition and Subtraction | |
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Multiplication | |
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Division | |
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Signed Notation | |
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Signed-Magnitude Notation | |
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Signed-Two's Complement Notation | |
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Binary Coded Decimal | |
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BCD Numeric Format | |
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Addition and Subtraction | |
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Multiplication and Division | |
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Specialized Arithmetic Hardware | |
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Historical Perspective: Coprocessors | |
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Pipelining | |
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Lookup Tables | |
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Historical Perspective: The Pentium Floating Point Bug | |
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Wallace Trees | |
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Floating Point Numbers | |
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Numeric Format | |
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Numeric Characteristics | |
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Addition and Subtraction | |
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Multiplication and Division | |
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Real World Example: The IEEE 754 Floating Point Standard | |
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Formats | |
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Denormalized Values | |
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Summary | |
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Problems | |
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Memory Organization | |
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Hierarchical Memory Systems | |
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Cache Memory | |
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Associative Memory | |
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Cache Memory with Associative Mapping | |
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Cache Memory with Direct Mapping | |
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Cache Memory with Set-Associative Mapping | |
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Practical Perspective: Mapping Strategies in Current CPUs | |
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Replacing Data in the Cache | |
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Writing Data to the Cache | |
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Cache Performance | |
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Virtual Memory | |
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Paging | |
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Segmentation | |
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Memory Protection | |
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Beyond the Basics of Cache and Virtual Memory | |
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Beyond the Basics of Cache Memory | |
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Practical Perspective: Cache Hierarchy in the Itanium Microprocessor | |
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Beyond the Basics of Virtual Memory | |
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Real World Example: Memory Management in a Pentium/Windows Personal Computer | |
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Summary | |
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Problems | |
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Input/Output Organization | |
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Asynchronous Data Transfers | |
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Source-Initiated Data Transfer | |
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Destination-Initiated Data Transfer | |
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Handshaking | |
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Programmed I/O | |
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New Instructions | |
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New Control Signals | |
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New States and RTL Code | |
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Modify the CPU Hardware for the New Instruction | |
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Make Sure Other Instructions Still Work | |
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Interrupts | |
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Transferring Data Between the CPU and I/O Devices | |
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Types of Interrupts | |
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Processing Interrupts | |
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Interrupt Hardware and Priority | |
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Implementing Interrupts Inside the CPU | |
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Direct Memory Access | |
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Incorporating Direct Memory Access (DMA) into a Computer System | |
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DMA Transfer Modes | |
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Modifying the CPU to Work with DMA | |
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I/O Processors | |
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Practical Perspective: The i960 I/O Processor with Built-in DMA | |
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Serial Communication | |
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Serial Communication Basics | |
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Universal Asynchronous Receiver/Transmitters (UARTs) | |
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Real World Example: Serial Communication Standards | |
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The RS-232-C Standard | |
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Practical Perspective: The RS-422 Serial Standard | |
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The Universal Serial Bus Standard | |
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Summary | |
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Problems | |
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Advanced Topics | |
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Reduced Instruction Set Computing | |
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RISC Rationale | |
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Fixed Length Instructions | |
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Limited Loading and Storing Instructions Access Memory | |
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Fewer Addressing Modes | |
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Instruction Pipeline | |
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Practical Perspective: Addressing Modes in the PowerPC 750 RISC CPU | |
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Large Number of Registers | |
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Hardwired Control Unit | |
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Delayed Loads and Branches | |
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Speculative Execution of Instructions | |
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Optimizing Compiler | |
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Separate Instruction and Data Streams | |
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RISC Instruction Sets | |
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Instruction Pipelines and Register Windows | |
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Instruction Pipelines | |
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Register Windowing and Renaming | |
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Practical Perspective: Register Windowing and Register Renaming in Real-World CPUs | |
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Instruction Pipeline Conflicts | |
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Data Conflicts | |
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Branch Conflicts | |
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RISC vs. CISC | |
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Real World Example: The Itanium Microprocessor | |
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Summary | |
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Problems | |
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Introduction to Parallel Processing | |
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Parallelism in Uniprocessor Systems | |
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Organization of Multiprocessor Systems | |
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Flynn's Classification | |
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System Topologies | |
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MIMD System Architectures | |
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Practical Perspective: The World's Largest Multicomputer? | |
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Practical Perspective: The Blue Gene Computer | |
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Communication in Multiprocessor Systems | |
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Fixed Connections | |
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Reconfigurable Connections | |
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Routing on Multistage Interconnection Networks | |
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Memory Organization in Multiprocessor Systems | |
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Shared Memory | |
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Cache Coherence | |
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Multiprocessor Operating Systems and Software | |
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Parallel Algorithms | |
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Parallel Bubble Sort | |
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Parallel Matrix Multiplication | |
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Alternative Parallel Architectures | |
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Dataflow Computing | |
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Systolic Arrays | |
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Neural Networks | |
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Summary | |
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Problems | |
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Index | |