| |
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| Preface to the Second Edition | |
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| Preface to the First Edition | |
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| Acknowledgments | |
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| Device Physics | |
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| Semiconductors | |
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| Generation and Recombination | |
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| Extrinsic Semiconductors | |
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| Diffusion and Drift | |
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| PN Junctions | |
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| Depletion Regions | |
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| PN Diodes | |
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| Schottky Diodes | |
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| Zener Diodes | |
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| Ohmic Contacts | |
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| Bipolar Junction Transistors | |
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| Beta | |
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| I-V Characteristics | |
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| MOS Transistors | |
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| Threshold Voltage | |
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| I-V Characteristics | |
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| JFET Transistors | |
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| Summary | |
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| Exercises | |
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| Semiconductor Fabrication | |
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| Silicon Manufacture | |
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| Crystal Growth | |
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| Wafer Manufacturing | |
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| The Crystal Structure of Silicon | |
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| Photolithography | |
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| Photoresists | |
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| Photomasks and Reticles | |
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| Patterning | |
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| Oxide Growth and Removal | |
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| Oxide Growth and Deposition | |
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| Oxide Removal | |
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| Other Effects of Oxide Growth and Removal | |
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| Local Oxidation of Silicon (LOCOS) | |
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| Diffusion and Ion Implantation | |
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| Diffusion | |
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| Other Effects of Diffusion | |
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| Ion Implantation | |
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| Silicon Deposition and Etching | |
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| Epitaxy | |
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| Polysilicon Deposition | |
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| Dielectric Isolation | |
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| Metallization | |
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| Deposition and Removal of Aluminum | |
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| Refractory Barrier Metal | |
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| Silicidation | |
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| Interlevel Oxide, Interlevel Nitride, and Protective Overcoat | |
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| Copper Metallization | |
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| Assembly | |
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| Mount and Bond | |
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| Packaging | |
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| Summary | |
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| Exercises | |
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| Representative Processes | |
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| Standard Bipolar | |
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| Essential Features | |
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| Fabrication Sequence | |
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| Starting Material | |
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| N-Buried Layer | |
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| Epitaxial Growth | |
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| Isolation Diffusion | |
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| Base Implant | |
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| Emitter Diffusion | |
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| Contact | |
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| Metallization | |
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| Protective Overcoat | |
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| Available Devices | |
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| NPN Transistors | |
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| PNP Transistors | |
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| Resistors | |
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| Capacitors | |
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| Process Extensions | |
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| Up-Down Isolation | |
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| Double-Level Metal | |
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| Schottky Diodes | |
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| High-Sheet Resistors | |
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| Super-Beta Transistors | |
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| Polysilicon-Gate CMOS | |
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| |
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| Essential Features | |
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| |
| |
| Fabrication Sequence | |
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| Starting Material | |
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| |
| Epitaxial Growth | |
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| N-Well Diffusion | |
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| Inverse Moat | |
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| Channel Stop Implants | |
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| LOCOS Processing and Dummy Gate Oxidation | |
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| Threshold Adjust | |
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| Deep-N+ | |
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| Polysilicon Deposition and Patterning | |
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| Source/Drain Implants | |
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| Contacts | |
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| |
| Metallization | |
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| Protective Overcoat | |
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| |
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| Available Devices | |
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| |
| NMOS Transistors | |
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| PMOS Transistors | |
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| Substrate PNP Transistors | |
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| Resistors | |
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| Capacitors | |
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| Process Extensions | |
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| Double-Level Metal | |
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| Shallow Trench Isolation | |
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| Silicidation | |
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| |
| Lightly Doped Drain (LDD) Transistors | |
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| Extended-Drain, High-Voltage Transistors | |
| |
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| |
| Analog BiCMOS | |
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| |
| |
| Essential Features | |
| |
| |
| |
| Fabrication Sequence | |
| |
| |
| Starting Material | |
| |
| |
| N-Buried Layer | |
| |
| |
| Epitaxial Growth | |
| |
| |
| N-Well Diffusion and | |
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| |
| Base Implant | |
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| Inverse Moat | |
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| |
| Channel Stop Implants | |
| |
| |
| LOCOS Processing and Dummy Gate Oxidation | |
| |
| |
| Threshold Adjust | |
| |
| |
| Polysilicon Deposition and Pattern | |
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| |
| Source/Drain Implants | |
| |
| |
| Metallization and Protective Overcoat | |
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| |
| Process Comparison | |
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| |
| |
| Available Devices | |
| |
| |
| NPN Transistors | |
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| |
| PNP Transistors | |
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| Resistors | |
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| Process Extensions | |
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| Advanced Metal Systems | |
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| Dielectric Isolation | |
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| Summary | |
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| Exercises | |
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| Failure Mechanisms | |
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| Electrical Overstress | |
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| Electrostatic Discharge (ESD) | |
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| Effects | |
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| Preventative Measures | |
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| Electromigration | |
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| Effects | |
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| Preventative Measures | |
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| Deep-N+ | |
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| Dielectric Breakdown | |
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| Effects | |
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| Preventative Measures | |
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| The Antenna Effect | |
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| Effects | |
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| Preventative Measures | |
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| Contamination | |
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| Dry Corrosion | |
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| Effects | |
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| Preventative Measures | |
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| Mobile Ion Contamination | |
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| Effects | |
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| Preventative Measures | |
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| Surface Effects | |
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| Hot Carrier Injection | |
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| Effects | |
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| Preventative Measures | |
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| Zener Walkout | |
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| |
| Effects | |
| |
| |
| Preventative Measures | |
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| |
| Avalanche-Induced Beta Degradation | |
| |
| |
| Effects | |
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| Preventative Measures | |
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| |
| Negative Bias Temperature Instability | |
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| |
| Effects | |
| |
| |
| Preventative Measures | |
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| |
| |
| Parasitic Channels and Charge Spreading | |
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| |
| Effects | |
| |
| |
| Preventative Measures (Standard Bipolar) | |
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| |
| Preventative Measures (CMOS and BiCMOS) | |
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| Parasitics | |
| |
| |
| |
| Substrate Debiasing | |
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| |
| Effects | |
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| |
| Preventative Measures | |
| |
| |
| |
| Minority-Carrier Injection | |
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| |
| Effects | |
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| |
| Preventative Measures (Substrate Injection) | |
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| |
| Preventative Measures (Cross-Injection) | |
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| |
| |
| Substrate Influence | |
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| |
| Effects | |
| |
| |
| Preventative Measures | |
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| Summary | |
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| |
| |
| Exercises | |
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| |
| |
| Resistors | |
| |
| |
| |
| Resistivity and Sheet Resistance | |
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| Resistor Layout | |
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| Resistor Variability | |
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| Process Variation | |
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| Temperature Variation | |
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| Nonlinearity | |
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| Contact Resistance | |
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| Resistor Parasitics | |
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| |
| |
| Comparison of Available Resistors | |
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| |
| Base Resistors | |
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| |
| |
| Emitter Resistors | |
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| |
| |
| Base Pinch Resistors | |
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| |
| High-Sheet Resistors | |
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| |
| Epi Pinch Resistors | |
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| Metal Resistors | |
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| |
| |
| Poly Resistors | |
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| |
| |
| NSD and PSD Resistors | |
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| |
| |
| N-Well Resistors | |
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| |
| |
| Thin-Film Resistors | |
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| |
| |
| Adjusting Resistor Values | |
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| |
| |
| Tweaking Resistors | |
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| |
| Sliding Contacts | |
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| |
| Sliding Heads | |
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| |
| Trombone Slides | |
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| |
| Metal Options | |
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| |
| |
| Trimming Resistors | |
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| |
| Fuses | |
| |
| |
| Zener Zaps | |
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| |
| EPROM Trims | |
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| |
| Laser Trims | |
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| Summary | |
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| Exercises | |
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| |
| |
| Capacitors and Inductors | |
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| |
| Capacitance | |
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| |
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| Capacitor Variability | |
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| Process Variation | |
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| |
| Voltage Modulation and Temperature Variation | |
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| |
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| Capacitor Parasitics | |
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| |
| |
| Comparison of Available Capacitors | |
| |
| |
| Base-Emitter Junction Capacitors | |
| |
| |
| MOS Capacitors | |
| |
| |
| Poly-Poly Capacitors | |
| |
| |
| Stack Capacitors | |
| |
| |
| Lateral Flux Capacitors | |
| |
| |
| High-Permittivity Capacitors | |
| |
| |
| |
| Inductance | |
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| |
| |
| Inductor Parasitics | |
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| |
| |
| Inductor Construction | |
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| |
| Guidelines for Integrating Inductors | |
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| |
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| Summary | |
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| |
| |
| Exercises | |
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| |
| |
| Matching of Resistors and Capacitors | |
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| |
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| Measuring Mismatch | |
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| |
| |
| Causes of Mismatch | |
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| |
| |
| Random Variation | |
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| |
| Capacitors | |
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| Resistors | |
| |
| |
| |
| Process Biases | |
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| |
| Interconnection Parasitics | |
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| |
| |
| Pattern Shift | |
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| |
| |
| Etch Rate Variations | |
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| |
| |
| Photolithographic Effects | |
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| |
| |
| Diffusion Interactions | |
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| |
| |
| Hydrogenation | |
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| |
| |
| Mechanical Stress and Package Shift | |
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| |
| |
| Stress Gradients | |
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| |
| Piezoresistivity | |
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| |
| Gradients and Centroids | |
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| |
| Common-Centroid Layout | |
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| |
| Location and Orientation | |
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| |
| Temperature Gradients and Thermoelectrics | |
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| |
| Thermal Gradients | |
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| |
| Thermoelectric Effects | |
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| |
| |
| Electrostatic Interactions | |
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| |
| Voltage Modulation | |
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| |
| Charge Spreading | |
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| |
| Dielectric Polarization | |
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| |
| Dielectric Relaxation | |
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| |
| |
| Rules for Device Matching | |
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| Rules for Resistor Matching | |
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| |
| |
| Rules for Capacitor Matching | |
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| |
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| Summary | |
| |
| |
| |
| Exercises | |
| |
| |
| |
| Bipolar Transistors | |
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| |
| |
| Topics in Bipolar Transistor Operation | |
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| |
| |
| Beta Rolloff | |
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| |
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| Avalanche Breakdown | |
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| |
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| Thermal Runaway and Secondary Breakdown | |
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| |
| |
| Saturation in NPN Transistors | |
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| Saturation in Lateral PNP Transistors | |
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| Parasitics of Bipolar Transistors | |
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| |
| |
| Standard Bipolar Small-Signal Transistors | |
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| |
| |
| The Standard Bipolar NPN Transistor | |
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| |
| Construction of Small-Signal NPN Transistors | |
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| |
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| The Standard Bipolar Substrate PNP Transistor | |
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| |
| Construction of Small-Signal Substrate PNP Transistors | |
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| |
| |
| The Standard Bipolar Lateral PNP Transistor | |
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| |
| Construction of Small-Signal Lateral PNP Transistors | |
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| |
| |
| High-Voltage Bipolar Transistors | |
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| |
| |
| Super-Beta NPN Transistors | |
| |
| |
| |
| CMOS and BiCMOS Small-Signal Bipolar Transistors | |
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| |
| |
| CMOS PNP Transistors | |
| |
| |
| |
| Shallow-Well Transistors | |
| |
| |
| |
| Analog BiCMOS Bipolar Transistors | |
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| |
| |
| Fast Bipolar Transistors | |
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| |
| |
| Polysilicon-Emitter Transistors | |
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| |
| |
| Oxide-Isolated Transistors | |
| |
| |
| |
| Silicon-Germanium Transistors | |
| |
| |
| |
| Summary | |
| |
| |
| |
| Exercises | |
| |
| |
| |
| Applications of Bipolar Transistors | |
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| |
| Power Bipolar Transistors | |
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| |
| |
| Failure Mechanisms of NPN Power Transistors | |
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| |
| Emitter Debiasing | |
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| |
| Thermal Runaway and Secondary Breakdown | |
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| |
| Kirk Effect | |
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| |
| |
| Layout of Power NPN Transistors | |
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| |
| The Interdigitated-Emitter Transistor | |
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| |
| The Wide-Emitter Narrow-Contact Transistor | |
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| |
| The Christmas-Tree Device | |
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| |
| The Cruciform-Emitter Transistor | |
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| |
| Power Transistor Layout in Analog BiCMOS | |
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| |
| Selecting a Power Transistor Layout | |
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| |
| |
| Power PNP Transistors | |
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| |
| |
| Saturation Detection and Limiting | |
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| |
| |
| Matching Bipolar Transistors | |
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| Random Variations | |
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| |
| |
| Emitter Degeneration | |
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| |
| |
| NBL Shadow | |
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| |
| |
| Thermal Gradients | |
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| |
| |
| Stress Gradients | |
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| |
| |
| Filler-Induced Stress | |
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| |
| |
| Other Causes of Systomatic Mismatch | |
| |
| |
| |
| Rules for Bipolar Transistor Matching | |
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| |
| |
| Rules for Matching Vertical Transistors | |
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| |
| |
| Rules for Matching Lateral Transistors | |
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| |
| |
| Summary | |
| |
| |
| |
| Exercises | |
| |
| |
| |
| Diodes | |
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| |
| |
| Diodes in Standard Bipolar | |
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| |
| |
| Diode-Connected Transistors | |
| |
| |
| |
| Zener Diodes | |
| |
| |
| Surface Zener Diodes | |
| |
| |
| Buried Zeners | |
| |
| |
| |
| Schottky Diodes | |
| |
| |
| |
| Power Diodes | |
| |
| |
| |
| Diodes in CMOS and BiCMOS Processes | |
| |
| |
| |
| CMOS Junction Diodes | |
| |
| |
| |
| CMOS and BiCMOS Schottky Diodes | |
| |
| |
| |
| Matching Diodes | |
| |
| |
| |
| Matching PN Junction Diodes | |
| |
| |
| |
| Matching Zener Diodes | |
| |
| |
| |
| Matching Schottky Diodes | |
| |
| |
| |
| Summary | |
| |
| |
| |
| Exercises | |
| |
| |
| |
| Field-Effect Transistors | |
| |
| |
| |
| Topics in MOS Transistor Operation | |
| |
| |
| |
| Modeling the MOS Transistor | |
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| |
| Device Transconductance | |
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| |
| Threshold Voltage | |
| |
| |
| |
| Parasitics of MOS Transistors | |
| |
| |
| Breakdown Mechanisms | |
| |
| |
| CMOS Latchup | |
| |
| |
| Leakage Mechanisms | |
| |
| |
| |
| Constructing CMOS Transistors | |
| |
| |
| |
| Coding the MOS Transistor | |
| |
| |
| Width and Length | |
| |
| |
| |
| N-Well and P-Well Processes | |
| |
| |
| |
| Channel Stop Implants | |
| |
| |
| |
| Threshold Adjust Implants | |
| |
| |
| |
| Scaling the Transistor | |
| |
| |
| |
| Variant Structures | |
| |
| |
| Serpentine Transistors | |
| |
| |
| Annular Transistors | |
| |
| |
| |
| Backgate Contacts | |
| |
| |
| |
| Floating-Gate Transistors | |
| |
| |
| |
| Principles of Floating-Gate Transistor Operation | |
| |
| |
| |
| Single-Poly Eeprom Memory | |
| |
| |
| |
| The JFET Transistor | |
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| |
| |
| Modeling the JFET | |
| |
| |
| |
| JFET Layout | |
| |
| |
| |
| Summary | |
| |
| |
| |
| Exercises | |
| |
| |
| |
| Applications of MOS Transistors | |
| |
| |
| |
| Extended-Voltage Transistors | |
| |
| |
| |
| LDD and DDD Transistors | |
| |
| |
| |
| Extended-Drain Transistors | |
| |
| |
| Extended-Drain NMOS Transistors | |
| |
| |
| Extended-Drain PMOS Transistors | |
| |
| |
| |
| Multiple Gate Oxides | |
| |
| |
| |
| Power MOS Transistors | |
| |
| |
| |
| MOS Safe Operating Area | |
| |
| |
| Electrical SOA | |
| |
| |
| Electrothermal SOA | |
| |
| |
| Rapid Transient Overload | |
| |
| |
| |
| Conventional MOS Power Transistors | |
| |
| |
| The Rectangular Device | |
| |
| |
| The Diagonal Device | |
| |
| |
| Computation of 501 RM | |
| |
| |
| Other Considerations | |
| |
| |
| Nonconventional Structures | |
| |
| |
| |
| DMOS Transistors | |
| |
| |
| The Lateral DMOS Transistor | |
| |
| |
| RESURF Transistors | |
| |
| |
| The DMOS NPN | |
| |
| |
| |
| MOS Transistor Matching | |
| |
| |
| |
| Geometric Effects | |
| |
| |
| Gate Area | |
| |
| |
| Gate Oxide Thickness | |
| |
| |
| Channel Length Modulation | |
| |
| |
| Orientation | |
| |
| |
| |
| Diffusion and Etch Effects | |
| |
| |
| Polysilicon Etch Rate Variations | |
| |
| |
| Diffusion Penetration of Polysilicon | |
| |
| |
| Contacts Over Active Gate | |
| |
| |
| Diffusions Near the Channel | |
| |
| |
| PMOS versus NMOS Transistors | |
| |
| |
| |
| Hydrogenation | |
| |
| |
| Fill Metal and MOS Matching | |
| |
| |
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| Thermal and Stress Effects | |
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| Oxide Thickness Gradients | |
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| Stress Gradients | |
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| Thermal Gradients | |
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| Common-Centroid Layout of MOS Transistors | |
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| Rules for MOS Transistor Matching | |
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| Summary | |
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| Exercises | |
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| Special Topics | |
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| Merged Devices | |
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| Flawed Device Mergers | |
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| Successful Device Mergers | |
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| Low-Risk Merged Devices | |
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| Medium-Risk Merged Devices | |
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| Devising New Merged Devices | |
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| The Role of Merged Devices in Analog BiCMOS | |
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| Guard Rings | |
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| Standard Bipolar Electron Guard Rings | |
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| Standard Bipolar Hole Guard Rings | |
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| Guard Rings in CMOS and BiCMOS Designs | |
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| Single-level Interconnection | |
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| Mock Layouts and Stick Diagrams | |
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| Techniques for Crossing Leads | |
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| Types of Tunnels | |
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| Constructing the Padring | |
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| Scribe Streets and Alignment Markers | |
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| Bondpads,Trimpads, and Testpads | |
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| ESD Structures | |
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| Zener Clamp | |
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| Two-Stage Zener Clamps | |
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| Buffered Zener Clamp | |
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| Clamp | |
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| Clamp | |
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| Antiparallel Diode Clamps | |
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| Grounded-Gate NMOS Clamps | |
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| CDM Clamps | |
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| Lateral SCR Clamps | |
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| Selecting ESD Structures | |
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| Exercises | |
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| Assembling the Die | |
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| Die Planning | |
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| Cell Area Estimation | |
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| Resistors | |
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| Capacitors | |
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| Vertical Bipolar Transistors | |
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| Lateral PNP Transistors | |
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| MOS Transistors | |
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| MOS Power Transistors | |
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| Computing Cell Area | |
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| Die Area Estimation | |
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| Gross Profit Margin | |
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| Floorplanning | |
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| Top-Level Interconnection | |
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| Principles of Channel Routing | |
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| Special Routing Techniques | |
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| Kelvin Connections | |
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| Noisy Signals and Sensitive Signals | |
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| Electromigration | |
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| Minimizing Stress Effects | |
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| Conclusion | |
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| Exercises | |
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| Appendices | |
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| Table of Acronyms Used in the Text | |
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| The Miller Indices of a Cubic Crystal | |
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| Sample Layout Rules | |
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| Mathematical Derivations | |
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| Sources for Layout Editor Software | |
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| Index | |