VHDL for Engineers

Name: VHDL for Engineers
Price: 49.99 USD
Availability: InStock
ISBN: 9780131424784

ISBN-10: 0131424785

ISBN-13: 9780131424784

Edition: 2009

Authors: Kenneth Short

List price: $226.65

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This book teaches readers how to design and simulate digital systems using the hardware description language, VHDL. Focus is placed on writing VHDL design decriptions, VHDL testbenches, and the steps in VHDL/PLD (programmable logic devices) design methodology. Topics include: Digital Design using VHDL and PLDs; Entities, Architectures, and Coding Styles; Signals and Data Types; Dataflow and Behavioral Style Combinational Design; Event-Driven Simulation; Testbenches for Combinational Designs; Latches and Flip-Flops; Mulitbit Latches, Registers, Counters, and Memory; Finite State Machines; ASM Charts and RTL Design; Subprograms; Packages; Testbenches for Sequential Systems; Modular Design and…

Book details

List price: $226.65
Copyright year: 2009
Publisher: Pearson Education
Publication date: 4/9/2008
Binding: Mixed Media
Pages: 720
Size: 7.40" wide x 9.40" long x 1.30" tall
Weight: 2.750
Language: English



Preface



Digital Design Using VHDL and PLDs



VHDL/PLD Design Methodology



Requirements Analysis and Specification



VHDL Design Description



Verification Using Simulation



Testbenches



Functional (Behavioral) Simulation



Programmable Logic Devices (PLDs)



SPLDs and the 22V10



Logic Synthesis for the Target PLD



Place-and-Route and Timing Simulation



Programming and Verifying a Target PLD



VHDL/PLD Design Methodology Advantages



VHDLrsquo;s Development



VHDL for Synthesis versus VHDL for Simulation



This Bookrsquo;s Primary Objective



Entities , Architectures , and Coding Styles



Design Units, Library Units, and Design Entities



Entity Declaration



VHDL Syntax Definitions



Port Modes



Architecture Body



Coding Styles



Synthesis Results versus Coding Style



Levels of Abstraction and Synthesis



Design Hierarchy and Structural Style



Signals and Data Types



Object Classes and Object Types



Signal Objects



Scalar Types



Type Std_Logic



Scalar Literals and Scalar Constants



Composite Types



Arrays



Types Unsigned and Signed



Composite Literals and Composite Constants



Integer Types