VHDL for Engineers

ISBN-10: 0131424785

ISBN-13: 9780131424784

Edition: 2009

Authors: Kenneth L. Short

List price: $199.80
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This book teaches readers how to design and simulate digital systems using the hardware description language, VHDL. Focus is placed on writing VHDL design decriptions, VHDL testbenches, and the steps in VHDL/PLD (programmable logic devices) design methodology. Topics include: Digital Design using VHDL and PLDs; Entities, Architectures, and Coding Styles; Signals and Data Types; Dataflow and Behavioral Style Combinational Design; Event-Driven Simulation; Testbenches for Combinational Designs; Latches and Flip-Flops; Mulitbit Latches, Registers, Counters, and Memory; Finite State Machines; ASM Charts and RTL Design; Subprograms; Packages; Testbenches for Sequential Systems; Modular Design and Hierarchy. More than 275 block diagrams, logic diagrams, and timing waveforms and 180+ program listings illustrate the design concepts. The book includes the Aldec Active-HDL(TM) 7.2 Student Edition Software. This book is suitable for anyone with a basic understanding of logic design and a minimal background in programming who desires to lean how to design digital systems using VHDL. No prior experience with VHDL is required.
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Book details

List price: $199.80
Copyright year: 2009
Publisher: Prentice Hall PTR
Publication date: 4/9/2008
Binding: Hardcover
Pages: 720
Size: 7.50" wide x 9.75" long x 1.25" tall
Weight: 3.102
Language: English

Digital Design Using VHDL and PLDs
VHDL/PLD Design Methodology
Requirements Analysis and Specification
VHDL Design Description
Verification Using Simulation
Functional (Behavioral) Simulation
Programmable Logic Devices (PLDs)
SPLDs and the 22V10
Logic Synthesis for the Target PLD
Place-and-Route and Timing Simulation
Programming and Verifying a Target PLD
VHDL/PLD Design Methodology Advantages
VHDLrsquo;s Development
VHDL for Synthesis versus VHDL for Simulation
This Bookrsquo;s Primary Objective
Entities , Architectures , and Coding Styles
Design Units, Library Units, and Design Entities
Entity Declaration
VHDL Syntax Definitions
Port Modes
Architecture Body
Coding Styles
Synthesis Results versus Coding Style
Levels of Abstraction and Synthesis
Design Hierarchy and Structural Style
Signals and Data Types
Object Classes and Object Types
Signal Objects
Scalar Types
Type Std_Logic
Scalar Literals and Scalar Constants
Composite Types
Types Unsigned and Signed
Composite Literals and Composite Constants
Integer Types
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