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Preface | |
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Introduction | |
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Logic Design | |
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A Brief Review of Number Systems | |
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Hexadecimal | |
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Binary Addition | |
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Signed Numbers | |
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Binary Subtraction | |
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Fractions, Mixed Numbers and Floating Point Representation | |
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Binary Coded Decimal (BCD) | |
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Other Codes | |
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Solved Problems | |
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Exercises | |
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Chapter 1 Test | |
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Logic Design | |
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Combinational Systems | |
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The Design Process for Combinational Systems | |
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Don 't Care Conditions | |
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The Development of Truth Tables | |
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Switching Algebra | |
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Definition of Switching Algebra | |
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Basic Properties of Switching Algebra | |
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Manipulation of Algebraic Functions | |
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Implementation of Functions with AND, OR, and NOT Gates | |
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The Complement | |
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From the Truth Table to Algebraic Expressions | |
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NAND, NOR, and Exclusive-OR Gates | |
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Simplification of Algebraic Expressions | |
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Manipulation of Algebraic Functions and NAND Gate Implementations | |
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Solved Problems | |
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Exercises | |
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Chapter 2 Test | |
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The Karnaugh Map | |
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Introduction to the Karnaugh Map | |
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Minimum Sum of Product Expressions Using the Karnaugh Map | |
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Don't Cares | |
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Product of Sums (POS) | |
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Five-Variable Maps | |
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Multiple-Output Problems | |
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Solved Problems | |
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Exercises | |
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Chapter 3 Test | |
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Designing Combinational Systems | |
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Iterative Systems | |
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Delay in Combinational Logic Circuits | |
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Adders | |
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Subtractors and Adder/Subtractors | |
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Comparators | |
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Binary Decoders | |
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Encoders and Priority Encoders | |
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Multiplexers and Demultiplexers | |
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Three-State Gates | |
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Gate Arrays-ROMs, PLAs, and PALs | |
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Designing with Read-Only Memories | |
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Designing with Programmable Logic Arrays | |
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Designing with Programmable Array Logic | |
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Testing and Simulation of Combinational Systems | |
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An Introduction to Verilog | |
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Larger Examples | |
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A One-Digit Decimal Adder | |
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A Driver for a Seven-Segment Display | |
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Solved Problems | |
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Exercises | |
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Chapter 4 Test | |
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Analysis of Sequential Systems | |
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State Tables and Diagrams | |
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Latches | |
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Flip Flops | |
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Analysis of Sequential Systems | |
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Solved Problems | |
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Exercises | |
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Chapter 5 Test | |
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The Design of Sequential Systems | |
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Flip Flop Design Techniques | |
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The Design of Synchronous Counters | |
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Design of Asynchronous Counters | |
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Derivation of State Tables and State Diagrams | |
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Solved Problems | |
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Exercises | |
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Chapter 6 Test | |
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Solving Larger Sequential Problems | |
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Shift Registers | |
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Counters | |
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Programmable Logic Devices (PLDs) | |
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Design Using ASM Diagrams | |
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One-Hot Encoding | |
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Verilog for Sequential Systems | |
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More Complex Examples | |
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Solved Problems | |
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Exercises | |
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Chapter 7 Test | |
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Computer Design | |
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Computer Organization | |
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Word Structure | |
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Instruction Formats and Word Size | |
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Data and Word Sizes | |
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Register Set | |
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Addressing Modes | |
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Instruction Set | |
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Data Movement Instructions | |
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Arithmetic Instructions | |
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Logic, Shift, and Rotate Instructions | |
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Branches | |
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Input/Output and Interrupts | |
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Instruction Timing | |
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Solved Problems | |
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Exercises | |
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Chapter 8 Test | |
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Computer Design Fundamentals | |
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Data Movement | |
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Control Sequence | |
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Design Description Language (DDL) | |
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Specification of DDL | |
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A Timing Refinement | |
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Designing a Controller | |
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Solved Problems | |
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Exercises | |
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Chapter 9 Test | |
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The Design of a Central Processing Unit | |
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Description of Model | |
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Memory and Register Set | |
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Addressing Modes | |
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Instruction Set of Model | |
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Control Sequence for Model | |
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Implementation of Model Control Sequence with a Hardwired Controller | |
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Model with a Slower Memory | |
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A Microprogrammed Controller | |
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Solved Problems | |
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Exercises | |
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Chapter 10 Test | |
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Beyond the Central Processing Unit | |
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Random Access Memory | |
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Cache Memory | |
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Secondary Memory | |
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Virtual Memory | |
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Interrupts | |
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Direct Memory Access | |
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Summary of Model Controller Design | |
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Answers to Selected Exercises | |
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Chapter Test Answers | |
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Index | |