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| Preface | |
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| Digital Principles | |
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| Number Systems and Codes | |
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| Decimal Odometer | |
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| Binary Odometer | |
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| Number Codes | |
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| Why Binary Numbers Are Used | |
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| Binary-to-Decimal Conversion | |
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| Microprocessors | |
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| Decimal-to-Binary Conversion | |
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| Hexadecimal Numbers | |
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| Hexadecimal-Binary Conversions | |
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| Hexadecimal-to-Decimal Conversion | |
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| Decimal-to-Hexadecimal Conversion | |
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| BCD Numbers | |
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| The ASCII Code | |
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| Gates | |
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| Inverters | |
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| Or Gates | |
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| And Gates | |
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| Boolean Algebra | |
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| More Logic Gates | |
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| Nor Gates | |
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| De Morgan's First Theorem | |
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| Nand Gates | |
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| De Morgan's Second Theorem | |
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| Exclusive-Or Gates | |
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| The Controlled Inverter | |
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| Exclusive-Nor Gates | |
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| TTL Circuits | |
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| Digital Integrated Circuits | |
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| 7400 Devices | |
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| TTL Characteristics | |
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| TTL Overview | |
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| And-Or-Invert Gates | |
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| Open-Collector Gates | |
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| Multiplexers | |
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| Boolean Algebra and Karnaugh Maps | |
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| Boolean Relations | |
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| Sum-of-Products Method | |
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| Algebraic Simplification | |
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| Karnaugh Maps | |
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| Pairs, Quads, and Octets | |
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| Karnaugh Simplifications | |
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| Don't-Care Conditions | |
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| Arithmetic-Logic Units | |
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| Binary Addition | |
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| Binary Subtraction | |
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| Half Adders | |
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| Full Adders | |
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| Binary Adders | |
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| Signed Binary Numbers | |
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| 2's Complement | |
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| 2's-Complement Adder-Subtracter | |
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| Flip-Flops | |
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| RS Latches | |
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| Level Clocking | |
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| D Latches | |
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| Edge-Triggered D Flip-Flops | |
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| Edge-Triggered JK Flip-Flops | |
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| JK Master-Slave Flip-Flop | |
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| Registers and Counters | |
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| Buffer Registers | |
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| Shift Registers | |
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| Controlled Shift Registers | |
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| Ripple Counters | |
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| Synchronous Counters | |
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| Ring Counters | |
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| Other Counters | |
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| Three-State Registers | |
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| Bus-Organized Computers | |
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| Memories | |
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| ROMs | |
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| PROMs and EPROMs | |
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| RAMs | |
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| A Small TTL Memory | |
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| Hexadecimal Addresses | |
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| SAP (Simple-as-Possible) Computers | |
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| SAP-1 | |
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| Architecture | |
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| Instruction Set | |
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| Programming SAP-1 | |
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| Fetch Cycle | |
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| Execution Cycle | |
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| The SAP-1 Microprogram | |
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| The SAP-1 Schematic Diagram | |
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| Microprogramming | |
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| SAP-2 | |
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| Bidirectional Registers | |
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| Architecture | |
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| Memory-Reference Instructions | |
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| Register Instructions | |
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| Jump and Call Instructions | |
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| Logic Instructions | |
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| Other Instructions | |
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| SAP-2 Summary | |
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| SAP-3 | |
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| Programming Model | |
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| MOV and MVI | |
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| Arithmetic Instructions | |
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| Increments, Decrements, and Rotates | |
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| Logic Instructions | |
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| Arithmetic and Logic Immediates | |
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| Jump Instructions | |
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| Extended-Register Instructions | |
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| Indirect Instructions | |
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| Stack Instructions | |
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| Programming Popular Microprocessors | |
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| Introduction to Microprocessors | |
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| Computer Hardware | |
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| Definition of a Microprocessor | |
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| Some Common Uses for Microprocessors | |
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| Microprocessors Featured in This Text | |
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| Access to Microprocessors | |
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| Programming and Languages | |
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| Relationship between Electronics and Programming | |
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| Programming | |
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| Fundamental Premise | |
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| Flowcharts | |
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| Programming Languages | |
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| Assembly Language | |
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| Worksheets | |
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| System Overview | |
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| New Concepts | |
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| Computer Architecture | |
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| Microprocessor Architecture | |
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| Specific Microprocessor Families | |
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| 6502 Family | |
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| 6800/6808 Family | |
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| 8080/8085/Z80 Family | |
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| 8086/8088 Family | |
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| Data Transfer Instructions | |
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| New Concepts | |
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| CPU Control Instructions | |
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| Data Transfer Instructions | |
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| Specific Microprocessor Families | |
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| 6502 Family | |
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| 6800/6808 Family | |
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| 8080/8085/Z80 Family | |
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| 8086/8088 Family | |
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| Addressing Modes--I | |
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| New Concepts | |
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| What Is an Addressing Mode? | |
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| The Paging Concept | |
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| Basic Addressing Modes | |
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| Specific Microprocessor Families | |
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| 6502 Family | |
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| 6800/6808 Family | |
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| 8080/8085/Z80 Family | |
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| 8086/8088 Family | |
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| Arithmetic and Flags | |
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| New Concepts | |
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| Microprocessors and Numbers | |
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| Arithmetic Instructions | |
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| Flag Instructions | |
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| Specific Microprocessor Families | |
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| 6502 Family | |
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| 6800/6808 Family | |
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| 8080/8085/Z80 Family | |
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| 8086/8088 Family | |
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| Logical Instructions | |
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| New Concepts | |
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| The and Instruction | |
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| The or Instruction | |
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| The Exclusive-or (EOR, XOR) Instruction | |
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| The not Instruction | |
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| The NEG (NEGate) Instruction | |
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| Specific Microprocessor Families | |
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| 6502 Family | |
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| 6800/6808 Family | |
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| 8080/8085/Z80 Family | |
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| 8086/8088 Family | |
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| Shift and Rotate Instructions | |
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| New Concepts | |
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| Rotating | |
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| Shifting | |
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| An Example | |
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| Specific Microprocessor Families | |
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| 6502 Family | |
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| 6800/6808 Family | |
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| 8080/8085/Z80 Family | |
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| 8086/8088 Family | |
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| Addressing Modes--II | |
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| New Concepts | |
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| Advanced Addressing Modes | |
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| Specific Microprocessor Families | |
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| 6502 Family | |
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| 6800/6808 Family | |
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| 8080/8085/Z80 Family | |
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| 8086/8088 Family | |
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| Branching and Loops | |
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| New Concepts | |
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| Unconditional Jumps | |
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| Conditional Branching | |
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| Compare and Test Instructions | |
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| Increment and Decrement Instructions | |
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| Nested Loops | |
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| Specific Microprocessor Families | |
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| 6502 Family | |
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| 6800/6808 Family | |
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| 8080/8085/Z80 Family | |
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| 8086/8088 Family | |
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| Subroutine and Stack Instructions | |
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| New Concepts | |
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| Stack and Stack Pointer | |
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| Branching versus Subroutines | |
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| How Do Subroutines Return? | |
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| Pushing and Popping Registers | |
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| Specific Microprocessor Families | |
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| 6502 Family | |
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| 6800/6808 Family | |
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| 8080/8085/Z80 Family | |
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| 8086/8088 Family | |
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| Microprocessor Instruction Set Tables | |
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| Expanded Table of 8085/8080 and Z80 (8080 Subset) Instructions Listed by Category | |
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| Mini Table of 8085/8080 and Z80 (8080 Subset) Instructions Listed by Category | |
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| Condensed Table of 8085/8080 and Z80 (8080) Instructions Listed by Category | |
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| Condensed Table of 8085/8080 and Z80 (8080 Subset) Instructions Listed by Op Code | |
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| Condensed Table of 8085/8080 and Z80 (8080 Subset) Instructions Listed Alphabetically by 8085/8080 Mnemonic | |
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| Condensed Table of 8085/8080 and Z80 (8080 Subset) Instructions Listed Alphabetically by Z80 Mnemonic | |
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| Expanded Table of 6800 Instructions Listed by Category | |
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| Short Table of 6800 Instructions Listed Alphabetically | |
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| Short Table of 6800 Instructions Listed by Category | |
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| Condensed Table of 6800 Instructions Listed by Category | |
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| Condensed Table of 6800 Instructions Listed Alphabetically | |
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| Condensed Table of 6800 Instructions Listed by Op Code | |
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| Expanded Table of 8086/8088 Instructions Listed by Category | |
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| Condensed Table of 8086/8088 Instructions Listed by Category | |
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| Condensed Table of 8086/8088 Instructions Listed Alphabetically | |
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| Expanded Table of 6502 Instructions Listed by Category | |
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| Short Table of 6502 Instructions Listed by Category | |
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| Condensed Table of 6502 Instructions Listed by Category | |
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| Condensed Table of 6502 Instructions Listed Alphabetically | |
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| Condensed Table of 6502 Instructions Listed by Op Code | |
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| Appendixes | |
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| The Analog Interface | |
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| Binary-Hexadecimal-Decimal Equivalents | |
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| 7400 Series TTL | |
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| Pinouts and Function Tables | |
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| SAP-1 Parts List | |
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| 8085 Instructions | |
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| Memory Locations: Powers of 2 | |
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| Memory Locations: 16K and 8K Intervals | |
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| Memory Locations: 4K Intervals | |
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| Memory Locations: 2K Intervals | |
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| Memory Locations: 1K Intervals | |
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| Programming Models | |
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| Answers to Odd-Numbered Problems | |
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| Index | |