Computer Organization and Design The Hardware/Software Interface

ISBN-10: 1558606041
ISBN-13: 9781558606043
Edition: 3rd 2004 (Revised)
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Description: This is a revision of the classic introduction to the field for all computer scientists and engineers. It includes improved examples of current architectures and updated pipelining and memory chapters to address modern processors.

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Book details

List price: $64.95
Edition: 3rd
Copyright year: 2004
Publisher: Elsevier Science & Technology Books
Publication date: 8/2/2004
Binding: Paperback
Pages: 656
Size: 7.75" wide x 8.75" long x 1.00" tall
Weight: 3.344
Language: English

This is a revision of the classic introduction to the field for all computer scientists and engineers. It includes improved examples of current architectures and updated pipelining and memory chapters to address modern processors.

David A. Patterson was the first in his family to graduate from college (1969 A.B UCLA), and he enjoyed it so much that he didn't stop until a PhD, (1976 UCLA). After 4 years developing a wafer-scale computer at Hughes Aircraft, he joined U.C. Berkeley in 1977. He spent 1979 at DEC working on the VAX minicomputer. He and colleagues later developed the Reduced Instruction Set Computer (RISC). By joining forces with IBM's 801 and Stanford's MIPS projects, RISC became widespread. In 1984 Sun Microsystems recruited him to start the SPARC architecture. In 1987, Patterson and colleagues wondered if tried building dependable storage systems from the new PC disks. This led to the popular Redundant Array of Inexpensive Disks (RAID). He spent 1989 working on the CM-5 supercomputer. Patterson and colleagues later tried building a supercomputer using standard desktop computers and switches. The resulting Network of Workstations (NOW) project led to cluster technology used by many startups. He is now working on the Recovery Oriented Computing (ROC) project. In the past, he served as Chair of Berkeley's CS Division, Chair and CRA. He is currently serving on the IT advisory committee to the U.S. President and has just been elected President of the ACM. All this resulted in 150 papers, 5 books, and the following honors, some shared with friends: election to the National Academy of Engineering; from the University of California: Outstanding Alumnus Award (UCLA Computer Science Department), McEntyre Award for Excellence in Teaching (Berkeley Computer Science), Distinguished Teaching Award (Berkeley); from ACM: fellow, SIGMOD Test of Time Award, Karlstrom Outstanding Educator Award; from IEEE: fellow, Johnson Information Storage Award, Undergraduate Teaching Award, Mulligan Education Medal, and von Neumann Medal.

John L. Hennessy is the president of Stanford University, where he has been a member of the faculty since 1977 in the departments of electrical engineering and computer science. Hennessy is a fellow of the IEEE and the ACM, a member of the National Academy of Engineering, the National Academy of Science, the American Academy of Arts and Sciences, and the Spanish Royal Academy of Engineering. He received the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and shared the John von Neumann award in 2000 with David Patterson. After completing the project in 1984, he took a one-year leave from the university to co-found MIPS Computer Systems, which developed one of the first commercial RISC microprocessors. After being acquired by Silicon Graphics in 1991, MIPS Technologies became an independent company in 1998, focusing on microprocessors for the embedded marketplace. As of 2004, over 300 million MIPS microprocessors have been shipped in devices ranging from video games and palmtop computers to laser printers and network switches. Hennessy's more recent research at Stanford focuses on the area of designing and exploiting multiprocessors. He helped lead the design of the DASH multiprocessor architecture, the first distributed shared-memory multiprocessors supporting cache coherency, and the basis for several commercial multiprocessor designs, including the Silicon Graphics Origin multiprocessors. Since becoming president of Stanford, revising and updating this text and the more advanced Computer Architecture: A Quantitative Approach has become a primary form of recreation and relaxation.

Prefacep. ix
Computer Abstractions and Technologyp. 2
Introductionp. 3
Below Your Programp. 11
Under the Coversp. 15
Real Stuff: Manufacturing Pentium 4 Chipsp. 28
Fallacies and Pitfallsp. 33
Concluding Remarksp. 35
Historical Perspective and Further Readingp. 36
Exercisesp. 36
Computers in the Real World: Information Technology for the 4 Billion without ITp. 44
Instructions: Language of the Computerp. 46
Introductionp. 48
Operations of the Computer Hardwarep. 49
Operands of the Computer Hardwarep. 52
Representing Instructions in the Computerp. 60
Logical Operationsp. 68
Instructions for Making Decisionsp. 72
Supporting Procedures in Computer Hardwarep. 79
Communicating with Peoplep. 90
MIPS Addressing for 32-Bit Immediates and Addressesp. 95
Translating and Starting a Programp. 106
How Compilers Optimizep. 116
How Compilers Work: An Introductionp. 121
A C Sort Example to Put It All Togetherp. 121
Implementing an Object-Oriented Languagep. 130
Arrays versus Pointersp. 130
Real Stuff: IA-32 Instructionsp. 134
Fallacies and Pitfallsp. 143
Concluding Remarksp. 145
Historical Perspective and Further Readingp. 147
Exercisesp. 147
Computers in the Real World: Helping Save Our Environment with Datap. 156
Arithmetic for Computersp. 158
Introductionp. 160
Signed and Unsigned Numbersp. 160
Addition and Subtractionp. 170
Multiplicationp. 176
Divisionp. 183
Floating Pointp. 189
Real Stuff: Floating Point in the IA-32p. 217
Fallacies and Pitfallsp. 220
Concluding Remarksp. 225
Historical Perspective and Further Readingp. 229
Exercisesp. 229
Computers in the Real World: Reconstructing the Ancient Worldp. 236
Assessing and Understanding Performancep. 238
Introductionp. 240
CPU Performance and Its Factorsp. 246
Evaluating Performancep. 254
Real Stuff: Two SPEC Benchmarks and the Performance of Recent Intel Processorsp. 259
Fallacies and Pitfallsp. 266
Concluding Remarksp. 270
Historical Perspective and Further Readingp. 272
Exercisesp. 272
Computers in The Real World: Moving People Faster and More Safelyp. 280
The Processor: Datapath and Controlp. 282
Introductionp. 284
Logic Design Conventionsp. 289
Building a Datapathp. 292
A Simple Implementation Schemep. 300
A Multicycle Implementationp. 318
Exceptionsp. 340
Microprogramming: Simplifying Control Designp. 346
An Introduction to Digital Design Using a Hardware Design Languagep. 346
Real Stuff: The Organization of Recent Pentium Implementationsp. 347
Fallacies and Pitfallsp. 350
Concluding Remarksp. 352
Historical Perspective and Further Readingp. 353
Exercisesp. 354
Computers in the Real World: Empowering the Disabledp. 366
Enhancing Performance with Pipeliningp. 368
An Overview of Pipeliningp. 370
A Pipelined Datapathp. 384
Pipelined Controlp. 399
Data Hazards and Forwardingp. 402
Data Hazards and Stallsp. 413
Branch Hazardsp. 416
Using a Hardware Description Language to Describe and Model a Pipelinep. 426
Exceptionsp. 427
Advanced Pipelining: Extracting More Performancep. 432
Real Stuff: The Pentium 4 Pipelinep. 448
Fallacies and Pitfallsp. 451
Concluding Remarksp. 452
Historical Perspective and Further Readingp. 454
Exercisesp. 454
Computers in the Real World: Mass Communication without Gatekeepersp. 464
Large and Fast: Exploiting Memory Hierarchyp. 466
Introductionp. 468
The Basics of Cachesp. 473
Measuring and Improving Cache Performancep. 492
Virtual Memoryp. 511
A Common Framework for Memory Hierarchiesp. 538
Real Stuff: The Pentium P4 and the AMD Opteron Memory Hierarchiesp. 546
Fallacies and Pitfallsp. 550
Concluding Remarksp. 552
Historical Perspective and Further Readingp. 555
Exercisesp. 555
Computers in the Real World: Saving the World's Art Treasuresp. 562
Storage, Networks, and Other Peripheralsp. 564
Introductionp. 566
Disk Storage and Dependabilityp. 569
Networksp. 580
Buses and Other Connections between Processors, Memory, and I/O Devicesp. 581
Interfacing I/O Devices to the Processor, Memory, and Operating Systemp. 588
I/O Performance Measures: Examples from Disk and File Systemsp. 597
Designing an I/O Systemp. 600
Real Stuff: A Digital Camerap. 603
Fallacies and Pitfallsp. 606
Concluding Remarksp. 609
Historical Perspective and Further Readingp. 611
Exercisesp. 611
Computers in the Real World: Saving Lives through Better Diagnosisp. 622
Multiprocessors and Clustersp. 2
Introductionp. 4
Programming Multiprocessorsp. 8
Multiprocessors Connected by a Single Busp. 11
Multiprocessors Connected by a Networkp. 20
Clustersp. 25
Network Topologiesp. 27
Multiprocessors Inside a Chip and Multithreadingp. 30
Real Stuff: The Google Cluster of PCsp. 34
Fallacies and Pitfallsp. 39
Concluding Remarksp. 42
Historical Perspective and Further Readingp. 47
Exercisesp. 55
Appendices
Assemblers, Linkers, and the SPIM Simulatorp. 2
Introductionp. 3
Assemblersp. 10
Linkersp. 18
Loadingp. 19
Memory Usagep. 20
Procedure Call Conventionp. 22
Exceptions and Interruptsp. 33
Input and Outputp. 38
SPIMp. 40
MIPS R2000 Assembly Languagep. 45
Concluding Remarksp. 81
Exercisesp. 82
The Basics of Logic Designp. 2
Introductionp. 3
Gates, Truth Tables, and Logic Equationsp. 4
Combinational Logicp. 8
Using a Hardware Description Languagep. 20
Constructing a Basic Arithmetic Logic Unitp. 26
Faster Addition: Carry Lookaheadp. 38
Clocksp. 47
Memory Elements: Flip-flops, Latches, and Registersp. 49
Memory Elements: SRAMs and DRAMsp. 57
Finite State Machinesp. 67
Timing Methodologiesp. 72
Field Programmable Devicesp. 77
Concluding Remarksp. 78
Exercisesp. 79
Mapping Control to Hardwarep. 2
Introductionp. 3
Implementing Combinational Control Unitsp. 4
Implementing Finite State Machine Controlp. 8
Implementing the Next-State Function with a Sequencerp. 21
Translating a Microprogram to Hardwarep. 27
Concluding Remarksp. 31
Exercisesp. 32
A Survey of RISC Architectures for Desktop, Server, and Embedded Computersp. 2
Introductionp. 3
Addressing Modes and Instruction Formatsp. 5
Instructions: The MIPS Core Subsetp. 9
Instructions: Multimedia Extensions of the Desktop/Server RISCsp. 16
Instructions: Digital Signal-Processing Extensions of the Embedded RISCsp. 19
Instructions: Common Extensions to MIPS Corep. 20
Instructions Unique to MIPS64p. 25
Instructions Unique to Alphap. 27
Instructions Unique to SPARC v.9p. 29
Instructions Unique to PowerPCp. 32
Instructions Unique to PA-RISC 2.0p. 34
Instructions Unique to ARMp. 36
Instructions Unique to Thumbp. 38
Instructions Unique to SuperHp. 39
Instructions Unique to M32Rp. 40
Instructions Unique to MIPS16p. 41
Concluding Remarksp. 43
Acknowledgmentsp. 46
Referencesp. 47
Indexp. 1
Glossaryp. 1
Further Readingp. 1
Table of Contents provided by Rittenhouse. All Rights Reserved.

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