SystemVerilog for Design A Guide to Using SystemVerilog for Hardware Design and Modeling

ISBN-10: 1402075308

ISBN-13: 9781402075308

Edition: 2004

List price: $130.00
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Description: SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs. This book, SystemVerilog for Design , addresses the first aspect of the SystemVerilog extensions to Verilog. Important modeling features are presented, such as two-state data types, enumerated types, user-defined types, structures, unions, and interfaces. Emphasis is placed on the proper usage of these enhancements for simulation and synthesis. A companion to this book, SystemVerilog for Verification , covers the second aspect of SystemVerilog.

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Book details

List price: $130.00
Copyright year: 2004
Publisher: Springer
Publication date: 6/30/2003
Binding: Hardcover
Pages: 402
Size: 6.50" wide x 9.50" long x 1.25" tall
Weight: 1.760
Language: English

Introduction to SystemVerilog
SystemVerilog Literal Values and Built-in Data Types
SystemVerilog User-Defined and Enumerated Data Types
SystemVerilog Arrays, Structures and Unions
SystemVerilog Procedural Blocks, Tasks and Functions
SystemVerilog Procedural Statements
Modeling Finite State Machines with SystemVerilog
SystemVerilog Design Hierarchy
SystemVerilog Interfaces
A Complete Design Modeled With SystemVerilog
Behavioral and Transaction Level Modeling
The SystemVerilog Formal Definition (BNF)
A History of SUPERLOG, The Beginning of SystemVerilog
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