Digital Design with CPLD Applications and VHDL

ISBN-10: 1401840302
ISBN-13: 9781401840303
Edition: 2nd 2005 (Revised)
Authors: Robert K. Dueck
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Description: This Second Edition continues to use programmable logic as the primary vehicle for teaching digital design principles, and maintains its cutting-edge status by updating to Altera?s newest Quartus II software, the most current method of digital  More...

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Book details

List price: $398.95
Edition: 2nd
Copyright year: 2005
Publisher: Delmar Cengage Learning
Publication date: 9/9/2011
Binding: Hardcover
Pages: 1024
Size: 8.50" wide x 10.75" long x 1.50" tall
Weight: 7.326
Language: English

This Second Edition continues to use programmable logic as the primary vehicle for teaching digital design principles, and maintains its cutting-edge status by updating to Altera?s newest Quartus II software, the most current method of digital design implementation. This Windows-based software allows users to design, test, and program CPLD designs in text-based (VHDL) and graphic (schematic entry) formats. The Second Edition introduces CPLDs earlier in the teaching sequence, laying a solid foundation for more advanced principles without neglecting underlying digital fundamentals such as Boolean algebra, logic minimization, and combinational and sequential circuits. VHDL and Quartus II applications are provided throughout.

Preface
Basic Principles of Digital Systems
Digital Versus Analog Electronics
Digital Logic Levels
The Binary Number System
Hexadecimal Numbers
Digital Waveforms
Logic Functions and Gates
Basic Logic Functions
Derived Logic Functions
DeMorgan's Theorems and Gate Equivalence
Logic Switches and LED Indicators
Enable and Inhibit Properties of Logic Gates
Integrated Circuit Logic Gates
Boolean Algebra and Combinational Logic
Boolean Expressions, Logic Diagrams, and Truth Tables
Sum-of-Products and Product-of-Sums Forms
Theorems of Boolean Algebra
Simplifying SOP and POS Expressions
Simplification by the Karnaugh Map Method
Simplification by DeMorgan Equivalent Gates
Universal Property of NAND/NOR Gates
Practical Circuit Implementation in SSI Logic
Pulsed Operation of Logic Circuits
A General Approach to Logic Circuit Design
Introduction to PLDs and Quartus II
What is a PLD?
Programmable Sum-of-Products Arrays
PAL Fuse Matrix and Combinational Outputs
PAL Outputs with Programmable Polarity
Programming CPLDs Using Quartus II
Quartus II Design Flow and Graphical User Interface
Creating a Quartus II Project and Block Diagram File
Compiling and Simulating a Design in Quartus II
Transferring a Design to a Target CPLD
Using the Quartus II Block Editor to Create a Hierarchical Design
Introduction to VHDL
VHDL Basics
Making a VHDL File in Quartus II
VHDL Syntax for Port, Mode, and Type
Signals in VHDL
Combinational Logic Functions
Decoders
Encoders
Multiplexers
Demultiplexers
Magnitude Comparators
Parity Generators and Checkers
Digital Arithmetic and Arithmetic Circuits
Digital Arithmetic
Representing Signed Binary Numbers
Signed Binary Arithmetic
Hexadecimal Arithmetic
Numeric and Alphanumeric Codes
Binary Adders and Subtractors
BCD Adders
Carry Generation in Quartus II
Introduction to Sequential Logic
Latches
NAND/NOR Latches
Gated Latches
Edge-Triggered D Flip-Flops
Edge-Triggered JK Flip-Flops
Edge-Triggered T Flip-Flops
Flip-Flops in PLDs (Registered Outputs)
Generic Array Logic
MAX 7000S CPLD
FLEX 10K CPLD
Counters and Shift Registers
Basic Concepts of Digital Counters
Synchronous Counters
Design of Synchronous Counters
Programming Binary Counters for CPLDs
Control Options for Synchronous Counters
Programming Presettable and Bidirectional Counters for CPLDs
Shift Registers
Programming Shift Registers in VHDL
Shift Register Counters
State Machine Design
State Machines
State Machines with No Control Inputs
State Machines with Control Inputs
Switch Debouncer for a Normally Open Pushbutton Switch
Unused States in State Machines
Traffic Light Controller
Logic Gate Circuitry
Electrical Characteristics of Logic Gates
Propagation Delay
Flip-Flop Timing Parameters
Fanout
Power Dissipation
Noise Margin
Interfacing TTL and CMOS Gates
Internal Circuitry of TTL Gates
Internal Circuitry of CMOS Gates
TTL and CMOS Variations
Interfacing Analog and Digital Circuits
Analog and Digital Signals
Digital-to-Analog Conversion
Analog-to-Digital Conversion
Data Acquisition
Memory Devices and Systems
Basic Memory Concepts
Random Access Read/Write Memory (RAM)
Read Only Memory (ROM)
Sequential Memory: FIFO and LIFO
Dynamic RAM Modules
Memory Systems
Introduction to Microprocessors
Basic Structure of a Microcomputer
Register Level Structure of a Microcomputer System
Tristate Busses in Altera CPLDs
Quartus II Implementation of the RISC8v1 MCU
Creating New Instructions (RISC8v2)
Branch Instructions (RISC8v3)
RISC8 Test Circuit
Possible Enhancements to RISC8v3 MCU
Appendices
Converting MAX+PLUS II Projects to Quartus II
Answers to Selected Odd-Numbered Problems
Index

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