Logic Synthesis and Verification Algorithms

Name: Logic Synthesis and Verification Algorithms
Price: 60.35 USD
Availability: InStock
ISBN: 9780792397465

ISBN-10: 0792397460

ISBN-13: 9780792397465

Edition: 1996

Authors: Gary D. Hachtel, Fabio Somenzi

List price: $99.99

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Description:

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics. A unique feature of this text is…

Book details

List price: $99.99
Copyright year: 1996
Publisher: Springer
Publication date: 6/30/1996
Binding: Hardcover
Pages: 564
Size: 7.01" wide x 10.00" long x 1.00" tall
Weight: 2.750
Language: English




Introduction



Introduction



A Quick Tour of Logic Synthesis with the Help of a Simple Example



Two Level Logic Synthesis



Boolean Algebras



Synthesis of Two-Level Circuits



Heuristic Minimization of Two-Level Circuits



Binary Decision Diagrams (BDDs)



Models of Sequential Systems



Models of Sequential Systems



Synthesis and Verification of Finite State Machines



Finite Automata



Multilevel Logic Synthesis



Multi-Level Logic Synthesis



Multi-Level Minimization



Automatic Test Generation for Combinational Circuits



Technology Mapping



ASCII Codes



Supplementary Problems


Bibliography


Index