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| About the Author | |
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| The Fundamentals | |
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| Why Use FPGAs? | |
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| Applications | |
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| Some Technology Background | |
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| Fusible-link Technology | |
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| FPGA Programming Technologies | |
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| Instant Summary | |
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| FPGA Architectures | |
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| More on Programming Technologies | |
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| SRAM-based Devices | |
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| Antifuse-based Devices | |
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| E[superscript 2]PROM/FLASH-based Devices | |
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| Hybrid FLASH-SRAM Devices | |
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| Fine-, Medium-, and Coarse-grained Architectures | |
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| Logic Blocks | |
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| MUX-based | |
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| LUT-based | |
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| LUT versus Distributed RAM versus SR | |
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| CLBs versus LABs versus Slices | |
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| Logic Cells/Logic Elements | |
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| Slicing and Dicing | |
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| CLBs and LABs | |
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| Distributed RAMs and Shift Registers | |
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| Embedded RAMs | |
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| Embedded Multipliers, Adders, etc. | |
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| Embedded Processor Cores | |
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| Hard Microprocessor Cores | |
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| Soft Microprocessor Cores | |
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| Clock Managers | |
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| Clock Trees | |
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| Clock Managers | |
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| General-purpose I/O | |
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| Configurable I/O Standards | |
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| Configurable I/O Impedances | |
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| Core versus I/O Supply Voltages | |
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| Gigabit Transceivers | |
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| Multiple Standards | |
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| Intellectual Property (IP) | |
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| Handcrafted IP | |
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| IP Core Generators | |
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| System Gates versus Real Gates | |
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| Instant Summary | |
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| Programming (Configuring) an FPGA | |
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| Configuration Cells | |
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| Antifuse-based FPGAs | |
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| SRAM-based FPGAs | |
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| Programming Embedded (Block) RAMs, Distributed RAMs, etc. | |
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| Multiple Programming Chains | |
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| Quickly Reinitializing the Device | |
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| Using the Configuration Port | |
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| Serial Load with FPGA as Master | |
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| Parallel Load with FPGA as Master | |
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| Parallel Load with FPGA as Slave | |
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| Serial Load with FPGA as Slave | |
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| Using the JTAG Port | |
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| Using an Embedded Processor | |
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| Instant Summary | |
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| FPGA vs. ASIC Designs | |
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| When You Switch from ASIC to FPGA Design, or Vice Versa | |
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| Coding Styles | |
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| Pipelining and Levels of Logic | |
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| Levels of Logic | |
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| Asynchronous Design Practices | |
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| Asynchronous Structures | |
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| Combinational Loops | |
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| Delay Chains | |
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| Clock Considerations | |
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| Clock Domains | |
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| Clock Balancing | |
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| Clock Gating versus Clock Enabling | |
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| PLLs and Clock Conditioning Circuitry | |
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| Reliable Data Transfer across Multiclock Domains | |
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| Register and Latch Considerations | |
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| Latches | |
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| Flip-flops with both "Set" and "Reset" Inputs | |
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| Global Resets and Initial Conditions | |
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| Resource Sharing (Time-Division Multiplexing) | |
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| Use It or Lose It! | |
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| But Wait, There's More | |
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| State Machine Encoding | |
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| Test Methodologies | |
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| Migrating ASIC Designs to FPGAs and Vice Versa | |
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| Alternative Design Scenarios | |
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| Instant Summary | |
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| "Traditional" Design Flows | |
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| Schematic-based Design Flows | |
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| Back-end Tools like Layout | |
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| CAE + CAD = EDA | |
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| A Simple (early) Schematic-driven ASIC Flow | |
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| A Simple (early) Schematic-driven FPGA Flow | |
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| Flat versus Hierarchical Schematics | |
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| Schematic-driven FPGA Design Flows Today | |
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| HDL-based Design Flows | |
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| Advent of HDL-based Flows | |
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| A Plethora of HDLs | |
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| Points to Ponder | |
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| Instant Summary | |
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| Other Design Flows | |
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| C/C++-based Design Flows | |
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| C versus C++ and Concurrent versus Sequential | |
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| SystemC-based Flows | |
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| Augmented C/C++-based Flows | |
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| Pure C/C++-based Flows | |
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| Different Levels of Synthesis Abstraction | |
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| Mixed-language Design and Verification Environments | |
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| DSP-Based Design Flows | |
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| Alternative DSP Implementations | |
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| FPGA-centric Design Flows for DSPs | |
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| Mixed DSP and VHDL/Verilog etc. Environments | |
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| Embedded Processor-based Design Flows | |
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| Hard versus Soft Cores | |
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| Partitioning a Design into Its Hardware and Software Components | |
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| Using an FPGA as Its Own Development Environment | |
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| Improving Visibility in the Design | |
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| A Few Coverification Alternatives | |
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| Instant Summary | |
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| Using Design Tools | |
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| Simulation Tools | |
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| Event-driven Logic Simulators | |
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| Logic Values and Different Logic Value Systems | |
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| Mixed-language Simulation | |
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| Alternative Delay Formats | |
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| Cycle-based Simulators | |
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| Choosing a Logic Simulator | |
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| Synthesis (Logic/HDL versus Physically Aware) | |
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| Logic/HDL Synthesis Technology | |
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| Physically Aware Synthesis Technology | |
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| Retiming, Replication, and Resynthesis | |
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| Timing Analysis | |
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| Static Timing Analysis | |
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| Statistical Static Timing Analysis | |
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| Verification in General | |
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| Verification IP | |
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| Verification Environments and Creating Testbenches | |
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| Analyzing Simulation Results | |
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| Formal Verification | |
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| Different Flavors of Formal Verification | |
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| Terminology and Definitions | |
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| Alternative Assertion/Property Specification Techniques | |
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| Static Formal versus Dynamic Formal | |
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| Miscellaneous | |
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| HDL to C Conversion | |
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| Code Coverage | |
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| Performance Analysis | |
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| Instant Summary | |
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| Choosing the Right Device | |
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| Choosing | |
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| Technology | |
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| Basic Resources and Packaging | |
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| General-purpose I/O Interfaces | |
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| Embedded Multipliers, RAMs, etc. | |
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| Embedded Processor Cores | |
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| Gigabit I/O Capabilities | |
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| IP Availability | |
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| Speed Grades | |
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| Future FPGA Developments | |
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| Instant Summary | |
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| Index | |