Microprocessor Architecture From Simple Pipelines to Chip Multiprocessors

ISBN-10: 0521769922

ISBN-13: 9780521769921

Edition: 2010

Authors: Jean-Loup Baer
List price: $150.00 Buy it from $17.72
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Book details

List price: $150.00
Copyright year: 2010
Publisher: Cambridge University Press
Publication date: 12/7/2009
Binding: Hardcover
Pages: 382
Size: 7.00" wide x 10.00" long x 1.00" tall
Weight: 2.068
Language: English

Jean-Loup Baer is Professor Emeritus of Computer Science and Engineering at the University of Washington, where he has been since 1969. Professor Baer is the author of Computer Systems Architecture and more than 100 refereed papers. He is a Guggenheim Fellow, an ACM Fellow, and an IEEE Fellow. Baer has held several editorial positions, including editor-in-chief of the Journal of VLSI and Computer Systems and editor of the IEEE Transactions on Computers, the IEEE Transactions on Parallel and Distributed Systems, and the Journal of Parallel and Distributed Computing. He has served as General Chair and Program Chair of several conferences, including ISCA and HPCA.

Preface
Introduction
A Quick View of Technological Advances
Performance Metrics
Performance Evaluation
Summary
Further Reading and Bibliographical Notes
Exercises
References
The Basics
Pipelining
Caches
Virtual Memory and Paging
Summary
Further Reading and Bibliographical Notes
Exercises
References
Superscalar Processors
From Scalar to Superscalar Processors
Overview of the Instruction Pipeline of the DEC Alpha 21164
Introducing Register Renaming, Reorder Buffer, and Reservation Stations
Overview of the Pentium P6 Microarchitecture
VLIW/EPIC Processors
Summary
Further Reading and Bibliographical Notes
Exercises
References
Front-End: Branch Prediction, Instruction Fetching, and Register Renaming
Branch Prediction
Sidebar: The DEC Alpha 21264 Branch Predictor
Instruction Fetching
Decoding
Register Renaming (a Second Look)
Summary
Further Reading and Bibliographical Notes
Exercises
Programming Projects
References
Back-End: Instruction Scheduling, Memory Access Instructions, and Clusters
Instruction Issue and Scheduling (Wakeup and Select)
Memory-Accessing Instructions
Back-End Optimizations
Summary
Further Reading and Bibliographical Notes
Exercises
Programming Project
References
The Cache Hierarchy
Improving Access to L1 Caches
Hiding Memory Latencies
Design Issues for Large Higher-Level Caches
Main Memory
Summary
Further Reading and Bibliographical Notes
Exercises
Programming Projects
References
Multiprocessors
Multiprocessor Organization
Cache Coherence
Synchronization
Relaxed Memory Models
Multimedia Instruction Set Extensions
Summary
Further Reading and Bibliographical Notes
Exercises
References
Multithreading and (Chip) Multiprocessing
Single-Processor Multithreading
General-Purpose Multithreaded Chip Multiprocessors
Special-Purpose Multithreaded Chip Multiprocessors
Summary
Further Reading and Bibliographical Notes
Exercises
References
Current Limitations and Future Challenges
Power and Thermal Management
Technological Limitations: Wire Delays and Pipeline Depths
Challenges for Chip Multiprocessors
Summary
Further Reading and Bibliographical Notes
References
Bibliography
Index
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