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Introduction: Number Systems and Conversion | |
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Digital Systems and Switching Circuits | |
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Number Systems and Conversion | |
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Binary Arithmetic | |
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Representation of Negative Numbers | |
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Binary Codes | |
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Boolean Algebra | |
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Introduction | |
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Basic Operations | |
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Boolean Expressions and Truth Tables | |
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Basic Theorems | |
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Commutative, Associative, and Distributive Laws | |
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Simplification Theorems | |
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Multiplying Out and Factoring | |
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DeMorgan's Laws | |
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Boolean Algebra (Cont) | |
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Multiplying Out and Factoring Expressions | |
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Exclusive-OR and Equivalence Operations | |
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The Consensus Theorem | |
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Algebraic Simplification of Switching Expressions | |
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Proving Validity of an Equation | |
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Applications of Boolean Algebra: Minterm and Maxterm Expressions | |
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Conversion of English Sentences to Boolean Equations | |
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Combinational Logic Design Using a Truth Table | |
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Minterm and Maxterm Expansions | |
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General Minterm and Maxterm Expansions | |
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Incompletely Specified Functions | |
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Examples of Truth Table Construction | |
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Design of Binary Adders | |
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Karnaugh Maps | |
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Minimum Forms of Switching Functions | |
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Two- and Three-Variable Karnaugh Maps | |
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Four-Variable Karnaugh Maps | |
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Determination of Minimum Expressions Using Essential Prime Implicants | |
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Five-Variable Karnaugh Maps | |
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Other Uses of Karnaugh Maps | |
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Other Forms of Karnaugh Maps | |
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Quine-McClusky Method | |
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Determination of Prime Implicants | |
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The Prime Implicant Chart | |
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Petrick's Method | |
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Simplification of Incompletely Specified Functions | |
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Simplification Using Map-Entered Variables | |
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Conclusion | |
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Multi-Level Gate Circuits: NAND and NOR Gates Multi-Level Gate Circuits | |
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NAND and NOR Gates | |
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Design of Two-Level Circuits Using NAND and NOR Gates | |
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Design of Multi-Level NAND and NOR Gate Circuits | |
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Circuit Conversion Using Alternative Gate Symbols | |
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Design of Two-Level, Multiple-Output Circuits Determination of Essential Prime Implicants for Multiple-Output Realization | |
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Multiple-Output NAND and NOR Circuits | |
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Combinational Circuit Design and Simulation Using Gates Review of Combinational Circuit Design | |
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Design of Circuits with Limited Gate Fan-In | |
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Gate Delays and Timing Diagrams | |
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Hazards in Combinational Logic | |
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Simulation and Testing of Logic Circuits | |
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Multiplexers, Decodes, and Programmable Logic Devices Introduction | |
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Multiplexers | |
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Three-State Buffers | |
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Decoders and Encoders | |
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Read-Only Memories | |
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Programmable Logic Devices | |
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Complex Programmable Logic Devices | |
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Field Programmable Gate Arrays | |
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Introduction to VHDL VHDL Description of Combinational Circuits | |
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VHDL Models for Multiplexers | |
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VHDL Modules | |
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Signals and Constants | |
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Arrays | |
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VHDL Operators | |
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Packages and Libraries | |
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IEEE Standard Logic | |
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Compilation and Simulation of VHDL Code | |
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Latches and Flip-Flops Introduction | |
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Set-Reset Latch | |
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Gated D Latch | |
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Edge-Triggered D Flip-Flop | |
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S-R Flip-Flop | |
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J-K Flip-Flop | |
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T Flip-Flop | |
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Flip-Flops with Additional Inputs | |
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Summary | |
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Registers and Counters Registers and Register Transfers | |
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Shift Registers | |
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Design of Binary Counters | |
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Counters for Other Sequences | |
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Counter Design Using S-R and J-K Flip-XFlops | |
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Derivation of Flip-Flop Input Equations-Summary | |
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Analysis of Clocked Sequential Circuits A Sequential Parity Checker | |
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Analysis by Signal Tracing and Timing Charts | |
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State Tables and Graphs | |
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General Models for Sequential Circuits | |
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Derivation of State Graphs and Tables | |
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Design of a Sequence Detector | |
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More Complex Design Problems | |
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Guidelines for Construction of State Graphs | |
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Serial Data Code Conversion | |
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Alphanumeric State Graph Notation | |
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Reduction of State Tables State Assignment Elimination of Redundant States | |
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Equivalent States | |
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Determination of State Equivalence Using an Implication Table | |
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Equivalent Sequential Circuits | |
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Incompletely Specified State Tables | |
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Derivation of Flip-Flop Input Equations | |
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Equivalent State Assignments | |
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Guidelines for State Assignment | |
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Using a One-Hot State Assignment | |
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Sequential Circuit Design | |
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Summary of Design Procedure for Sequential Circuits | |
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Design Example-Code Converter | |
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Design of Iterative Circuits | |
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Design of Sequential Circuits Using ROMs and PLAs | |
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Sequential Circuit Design Using CPLDs | |
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Sequential Circuit Design Using FPGAs | |
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Simulation and Testing of Sequential Circuits | |
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Overview of Computer-Aided Design | |
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VHDL for Sequential Logic | |
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Modeling Flip-Flops Using VHDL Processes | |
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Modeling Registers and Counters Using VHDL Processes | |
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Modeling Combinational Logic Using VHDL Processes | |
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Modeling a Sequential Machine | |
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Synthesis of VHDL Code | |
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More About Processes and Sequential Statements | |
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Circuits for Arithmetic Operations | |
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Serial Adder with Accumulator | |
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Design of a Parallel Multiplier /Design of a Binary Divider | |
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State Machine Design with SM Charts State Machine Charts | |
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Derivation of SM Charts | |
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Realization of SM Charts | |
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VHDL for Digital System Design | |
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VHDL Code for a Serial Adder | |
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VHDL Code for a Binary Multiplier | |
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VHDL Code for a Binary Divider | |
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VHDL Code for a Dice Game Simulator | |
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Concluding Remarks | |
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Appendices MOS and CMOS Logic | |
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VHDL Language Summary /Proofs of Theorems | |
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References | |
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Answers to Selected Study Guide Questions and Problems | |
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Index | |