Embedded System Design A Unified Hardware/Software Introduction

ISBN-10: 0471386782
ISBN-13: 9780471386780
Edition: 2002
List price: $179.95
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Description: The authors present software and hardware design in a unified way in this introductory text to embedded systems design. They cover the trends and challenges in the field and discuss the modern tools that are used in the design of embedded systems.

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Book details

List price: $179.95
Copyright year: 2002
Publisher: John Wiley & Sons, Incorporated
Publication date: 10/17/2001
Binding: Hardcover
Pages: 352
Size: 7.50" wide x 9.50" long x 0.75" tall
Weight: 1.804

The authors present software and hardware design in a unified way in this introductory text to embedded systems design. They cover the trends and challenges in the field and discuss the modern tools that are used in the design of embedded systems.

Preface
Purpose
Coverage
How to Use This Book
Laboratory
Additional Materials
Acknowledgments
About the Authors
Introduction
Embedded Systems Overview
Design Challenge--Optimizing Design Metrics
Common Design Metrics
The Time-to-Market Design Metric
The NRE and Unit Cost Design Metrics
The Performance Design Metric
Processor Technology
General-Purpose Processors--Software
Single-Purpose Processors--Hardware
Application-Specific Processors
IC Technology
Full-Custom/VLSI
Semicustom ASIC (Gate Array and Standard Cell)
PLD
Trends
Design Technology
Compilation/Synthesis
Libraries/IP
Test/Verification
More Productivity Improvers
Trends
Trade-offs
Design Productivity Gap
Summary and Book Outline
References and Further Reading
Exercises
Custom Single-Purpose Processors: Hardware
Introduction
Combinational Logic
Transistors and Logic Gates
Basic Combinational Logic Design
RT-Level Combinational Components
Sequential Logic
Flip-Flops
RT-Level Sequential Components
Sequential Logic Design
Custom Single-Purpose Processor Design
RT-Level Custom Single-Purpose Processor Design
Optimizing Custom Single-Purpose Processors
Optimizing the Original Program
Optimizing the FSMD
Optimizing the Datapath
Optimizing the FSM
Summary
References and Further Reading
Exercises
General-Purpose Processors: Software
Introduction
Basic Architecture
Datapath
Control Unit
Memory
Operation
Instruction Execution
Pipelining
Superscalar and VLIW Architectures
Programmer's View
Instruction Set
Program and Data Memory Space
Registers
I/O
Interrupts
Example: Assembly-Language Programming of Device Drivers
Operating System
Development Environment
Design Flow and Tools
Example: Instruction-Set Simulator for a Simple Processor
Testing and Debugging
Application-Specific Instruction-Set Processors (ASIPs)
Microcontrollers
Digital Signal Processors (DSP)
Less-General ASIP Environments
Selecting a Microprocessor
General-Purpose Processor Design
Summary
References and Further Reading
Exercises
Standard Single-Purpose Processors: Peripherals
Introduction
Timers, Counters, and Watchdog Timers
Timers and Counters
Example: Reaction Timer
Watchdog Timers
Example: ATM Timeout Using a Watchdog Timer
UART
Pulse Width Modulators
Overview
Example: Controlling a DC Motor Using a PWM
LCD Controllers
Overview
Example: LCD Initialization
Keypad Controllers
Stepper Motor Controllers
Overview
Example: Using a Stepper Motor Driver
Example: Controlling a Stepper Motor Directly
Analog-to-Digital Converters
Example: Successive Approximation
Real-Time Clocks
Summary
References and Further Reading
Exercises
Memory
Introduction
Memory Write Ability and Storage Permanence
Write Ability
Storage Permanence
Trade-offs
Common Memory Types
Introduction to "Read-Only" Memory--ROM
Mask-Programmed ROM
OTP ROM--One-Time Programmable ROM
EPROM--Erasable Programmable ROM
EEPROM--Electrically Erasable Programmable ROM
Flash Memory
Introduction to Read-Write Memory--RAM
SRAM--Static RAM
DRAM--Dynamic RAM
PSRAM--Pseudo-Static RAM
NVRAM--Nonvolatile RAM
Example: HM6264 and 27C256 RAM/ROM Devices
Example: TC55V2325FF-100 Memory Device
Composing Memory
Memory Hierarchy and Cache
Cache Mapping Techniques
Cache-Replacement Policy
Cache Write Techniques
Cache Impact on System Performance
Advanced RAM
The Basic DRAM
Fast Page Mode DRAM (FPM DRAM)
Extended Data Out DRAM (EDO DRAM)
Synchronous (S) and Enhanced Synchronous (ES) DRAM
Rambus DRAM (RDRAM)
DRAM Integration Problem
Memory Management Unit (MMU)
Summary
References and Further Reading
Exercises
Interfacing
Introduction
Communication Basics
Basic Terminology
Basic Protocol Concepts
Example: The ISA Bus Protocol--Memory Access
Microprocessor Interfacing: I/O Addressing
Port and Bus-Based I/O
Memory-Mapped I/O and Standard I/O
Example: The ISA Bus Protocol--Standard I/O
Example: A Basic Memory Protocol
Example: A Complex Memory Protocol
Microprocessor Interfacing: Interrupts
Microprocessor Interfacing: Direct Memory Access
Example: DMA I/O and the ISA Bus Protocol
Arbitration
Priority Arbiter
Daisy-Chain Arbitration
Network-Oriented Arbitration Methods
Example: Vectored Interrupt Using an Interrupt table
Multilevel Bus Architectures
Advanced Communication Principles
Parallel Communication
Serial Communication
Wireless Communication
Layering
Error Detection and Correction
Serial Protocols
I[superscript 2]C
CAN
FireWire
USB
Parallel Protocols
PCI Bus
ARM Bus
Wireless Protocols
IrDA
Bluetooth
IEEE 802.11
Summary
References and Further Reading
Exercises
Digital Camera Example
Introduction
Introduction to a Simple Digital Camera
User's Perspective
Designer's Perspective
Requirements Specification
Nonfunctional Requirements
Informal Functional Specification
Refined Functional Specification
Design
Microcontroller Alone
Microcontroller and CCDPP
Microcontroller and CCDPP/Fixed-Point DCT
Microcontroller and CCDPP/DCT
Summary
References and Further Reading
Exercises
State Machine and Concurrent Process Models
Introduction
Models vs. Languages, Text vs. Graphics
Models vs. Languages
Textual Languages vs. Graphical Languages
An Introductory Example
A Basic State Machine Model: Finite-State Machines
Finite-State Machine with Datapath Model: FSMD
Using State Machines
Describing a System as a State Machine
Comparing State Machine and Sequential Program Models
Capturing State Machines in Sequential Programming Language
HCFSM and the Statecharts Language
Program-State Machine Model (PSM)
The Role of an Appropriate Model and Language
Concurrent Process Model
Concurrent Processes
Process Create and Terminate
Process Suspend and Resume
Process Join
Communication among Processes
Shared Memory
Message Passing
Synchronization among Processes
Condition Variables
Monitors
Implementation
Creating and Terminating Processes
Suspending and Resuming Processes
Joining a Process
Scheduling Processes
Dataflow Model
Real-Time Systems
Windows CE
QNX
Summary
References and Further Reading
Exercises
Control Systems
Introduction
Open-Loop and Closed-Loop Control Systems
Overview
A First Example: An Open-Loop Automobile Cruise Controller
A Second Example: A Closed-Loop Automobile Cruise Controller
General Control Systems and PID Controllers
Control Objectives
Modeling Real Physical Systems
Controller Design
Software Coding of a PID Controller
PID Tuning
Practical Issues Related to Computer-Based Control
Quantization and Overflow Effects
Aliasing
Computation Delay
Benefits of Computer-Based Control Implementations
Repeatability, Reproducability, and Stability
Programmability
Summary
References and Further Reading
Exercises
IC Technology
Introduction
Full-Custom (VLSI) IC Technology
Semi-Custom (ASIC) IC Technology
Gate Array Semi-Custom IC Technology
Standard Cell Semi-Custom IC Technology
Programmable Logic Device (PLD) IC Technology
Summary
References and Further Reading
Exercises
Design Technology
Introduction
Automation: Synthesis
"Going up": The Parallel Evolution of Compilation and Synthesis
Synthesis Levels
Logic Synthesis
Register-Transfer Synthesis
Behavioral Synthesis
System Synthesis and Hardware/Software Codesign
Temporal and Spatial Thinking
Verification: Hardware/Software Co-Simulation
Formal Verification and Simulation
Simulation Speed
Hardware-Software Co-Simulation
Emulators
Reuse: Intellectual Property Cores
Hard, soft and firm cores
New Challenges Posed by Cores to Processor Providers
New Challenges Posed by Cores to Processor Users
Design Process Models
Summary
Book Summary
References and Further Reading
Exercises
Online Resources
Introduction
Summary of the ESD Web Page
Lab Resources
About the Book Cover
Outdoors
Indoors
Index

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