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| Preface | |
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| Table of Contents | |
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| An Overview of VLSI | |
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| Complexity and Design | |
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| Basic Concepts | |
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| Plan of the Book | |
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| General References | |
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| Silicon Logic | |
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| Logic Design with MOSFETs | |
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| Ideal Switches and Boolean Operations | |
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| MOSFETs as Switches | |
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| Basic Logic Gates in CMOS | |
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| Complex Logic Gates in CMOS | |
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| Transmission Gate Circuits | |
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| Clocking and Dataflow Control | |
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| Further Reading | |
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| Problems | |
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| Physical Structure of CMOS Integrated Circuits | |
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| Integrated Circuit Layers | |
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| MOSFETs | |
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| CMOS Layers | |
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| Designing FET Arrays | |
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| References for Further Reading | |
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| Problems | |
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| Fabrication of CMOS Integrated Circuits | |
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| Overview of Silicon Processing | |
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| Material Growth and Deposition | |
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| Lithography | |
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| The CMOS Process Flow | |
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| Design Rules | |
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| Further Reading | |
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| Elements of Physical Design | |
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| Basic Concepts | |
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| Layout of Basic Structures | |
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| Cell Concepts | |
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| FET Sizing and the Unit Transistor | |
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| Physical Design of Logic Gates | |
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| Design Hierarchies | |
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| References for Further Reading | |
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| The Logic-Electronics Interface | |
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| Electrical Characteristics of MOSFETs | |
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| MOS Physics | |
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| nFET Current-Voltage Equations | |
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| The FET RC Model | |
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| pFET Characteristics | |
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| Modeling of Small MOSFETs | |
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| References for Further Reading | |
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| Problems | |
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| Electronic Analysis of CMOS Logic Gates | |
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| DC Characteristics of the CMOS Inverter | |
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| Inverter Switching Characteristics | |
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| Power Dissipation | |
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| DC Characteristics: NAND and NOR Gates | |
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| NAND and NOR Transient Response | |
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| Analysis of Complex Logic Gates | |
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| Gate Design for Transient Performance | |
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| Transmission Gates and Pass Transistors | |
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| Comments on SPICE Simulations | |
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| References for Further Study | |
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| Problems | |
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| Designing High-Speed CMOS Logic Networks | |
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| Gate Delays | |
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| Driving Large Capacitive Loads | |
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| Logical Effort | |
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| BiCMOS Drivers | |
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| Books for Further Reading | |
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| Problems | |
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| Advanced Techniques in CMOS Logic Circuits | |
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| Mirror Circuits | |
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| Pseudo-nMOS | |
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| Tri-State Circuits | |
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| Clocked CMOS | |
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| Dynamic CMOS Logic Circuits | |
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| Dual-Rail Logic Networks | |
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| Additional Reading | |
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| Problems | |
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| The Design of VLSI Systems | |
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| System Specifications Using Verilog HDL | |
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| Basic Concepts | |
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| Structural Gate-Level Modeling | |
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| Switch-Level Modeling | |
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| Design Hierarchies | |
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| Behavioral and RTL Modeling | |
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| References | |
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| Problems | |
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| General VLSI System Components | |
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| Multiplexors | |
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| Binary Decoders | |
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| Equality Detectors and Comparators | |
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| Priority Encoder | |
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| Shift and Rotation Operations | |
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| Latches | |
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| D Flip-Flop | |
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| Registers | |
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| The Role of Synthesis | |
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| References for Further Study | |
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| Problems | |
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| Arithmetic Circuits in CMOS VLSI | |
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| Bit Adder Circuits | |
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| Ripple-Carry Adders | |
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| Carry Look-Ahead Adders | |
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| Other High-Speed Adders | |
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| Multipliers | |
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| Summary | |
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| References | |
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| Problems | |
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| Memories and Programmable Logic | |
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| The Static RAM | |
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| SRAM Arrays | |
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| Dynamic RAMs | |
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| ROM Arrays | |
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| Logic Arrays | |
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| References | |
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| Problems | |
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| System-Level Physical Design | |
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| Large-Scale Physical Design | |
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| Interconnect Delay Modeling | |
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| Crosstalk | |
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| Interconnect Scaling | |
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| Floorplanning and Routing | |
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| Input and Output Circuits | |
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| Power Distribution and Consumption | |
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| Low-Power Design Considerations | |
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| References for Further Study | |
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| Problems | |
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| VLSI Clocking and System Design | |
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| Clocked Flip-flops | |
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| CMOS Clocking Styles | |
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| Pipelined Systems | |
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| Clock Generation and Distribution | |
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| System Design Considerations | |
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| References for Advanced Reading | |
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| Reliability and Testing of VLSI Circuits | |
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| General Concepts | |
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| CMOS Testing | |
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| Test Generation Methods | |
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| Summary | |
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| References | |
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| Index | |