Verilog for Digital Design

ISBN-10: 0470052627
ISBN-13: 9780470052624
Edition: 2007
List price: $59.95
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Description: VHSIC Hardware Description Language is commonly used as a design entry language. This book features numerous examples and tips in the margins. The author focuses on the application and use of the language, rather than just teaching the basics of the  More...

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Book details

List price: $59.95
Copyright year: 2007
Publisher: John Wiley & Sons, Incorporated
Publication date: 7/9/2007
Binding: Paperback
Pages: 192
Size: 7.50" wide x 9.00" long x 0.50" tall
Weight: 0.682
Language: English

VHSIC Hardware Description Language is commonly used as a design entry language. This book features numerous examples and tips in the margins. The author focuses on the application and use of the language, rather than just teaching the basics of the language.

Preface
To Those About to Study Verilog
To Teachers of Verilog
About the Book
Chapter Overview
Accompanying Resources
Formatting
Acknowledgments
About the Authors
Contents
Introduction
Digital Systems
Hardware Description Languages
HDLs for Design and Synthesis
Combinational Logic Design
AND, OR, and NOT Gates
Modules and Ports
Module Procedures-always
Simulation and Testbenches-A First Look
Variables and nets
Module procedures-initial
Delay control
Comments
Combinational Circuit Structure
Module Instantiations
Port Connections
Simulating The Circuit
Top-Down Design-Combinational Behavior to Structure
Procedures with If-Else Statements
Multiple Module Descriptions for One Module
Common Pitfalls
Missing inputs from event control expression
Outputs not assigned on every pass
Hierarchical Circuits
Using Modules as Instances
Built-In Logic Gates
Sequential Logic Design
Register Behavior
Vectors
Constant Numbers
Synchronous Storage Using a reg Variable
Testbenches with Clocks
Common Pitfalls
Using an always procedure instead of an initial procedure
Not including any delay control or event control in an always procedure
Not initializing all input ports
Not declaring an identifier used in a port connection
Finite-State Machines (FSMs)-Sequential Behavior
Multiple Always Procedures and Shared Variables
Parameters (Constants)
Procedures with Case Statements
Self-Checking Testbenches
Top-Down Design-FSMs to Controller Structure
Common Pitfall
Not assigning outputs in every state
More Simulation Concepts
The Simulation Cycle
Scheduled Events
Resets
Describing Safe FSMs
Datapath Components
Multifunction Registers
Continuous Assignment Statement
Common Pitfall
Not using a begin-end block with every if statement
Adders
Built-In Arithmetic Operations
Concatenation
Blocking Versus Non-Blocking Assignments
Left-Side Concatenation
Shift Registers
Procedures with For Loop Statements
Integer Variables
Relational, Logical, and Equality Operators
File Input and Output
Functions and tasks
File input and output procedures
While loops
Common Pitfall
Creating a loop that cannot be unrolled during synthesis
Comparators
Unsigned and Signed Numbers
Common Pitfall
Unintentional use of one of Verilog's many automatic conversions
Register Files
Using High-Impedance Values
Conditional Operator "?"
Multiple Drivers of One Net
Arrays
Common Pitfall
Confusing bitwise and logical operators
Register-Transfer Level (RTL) Design
High-Level State Machine (HLSM) Behavior
Top-Down Design-HLSM to Controller and Datapath
Describing a State Machine using One Procedure
Improving Timing Realism
Delay Control on Right Side of Assignment Statements
Algorithmic-Level Behavior
Top-Down Design-Converting Algorithmic-Level Behavior to RTL
Automated Synthesis from the Algorithmic-Level
Simulation Speed
Memory
Verilog Mini-Reference
Basic Syntax
Comments
Identifiers
Keywords
Numbers
Integer Constant
Real Constant
Strings
Declarations
Net (Wire)
Module
Ports
Parameter
Local Parameter
Variable (Reg)
Statements
Assignment Statement
Blocking Assignment
Non-blocking Assignment
Continuous Assignment
Case Statement
If-Else Statement
Loop Statement
For Loop
Repeat Loop
While Loop
Null
Procedure
Always Procedure
Initial Procedure
Module Instantiation
Port Connection
Parameter Assignment
Timing control
Delay Control
Event Control
Timescale Directive
Wait Statement
Operators
Arithmetic
Bitwise
Concatenation
Conditional
Equality
Logical
Reduction
Relational
Shift
Operator Precedence
System Tasks and Functions
$display and $write
File Input and Output
$fopen
$feof
$fgetc
$fclose
$fdisplay and $fwrite
$readmemb and $readmemh
$signed and $unsigned
$time
Common Data Types
Array
Integer
Signed
Vector
Index

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