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| Preface | |
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| An Overview of Microelectronic Fabrication | |
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| A Historical Perspective | |
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| An Overview of Monolithic Fabrication Processes and Structures | |
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| Metal-Oxide-Semiconductor (MOS) Processes | |
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| Basic Bipolar Processing | |
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| Safety | |
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| Lithography | |
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| The Photolithographic Process | |
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| Etching Techniques | |
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| Photomask Fabrication | |
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| Exposure Systems | |
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| Exposure Sources | |
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| Optical and Electron Microscopy | |
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| Further Reading | |
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| Thermal Oxidation of Silicon | |
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| The Oxidation Process | |
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| Modeling Oxidation | |
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| Factors Influencing Oxidation Rate | |
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| Dopant Redistribution During Oxidation | |
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| Masking Properties of Silicon Dioxide | |
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| Technology of Oxidation | |
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| Oxide Quality | |
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| Selective Oxidation and Shallow Trench Formation | |
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| Oxide Thickness Characterization | |
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| Process Simulation | |
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| Diffusion | |
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| The Diffusion Process | |
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| Mathematical Model for Diffusion | |
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| The Diffusion Coefficient | |
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| Successive Diffusions | |
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| Solid-Solubility Limits | |
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| Junction Formation and Characterization | |
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| Sheet Resistance | |
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| Generation-Depth and Impurity Profile Measurement | |
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| Diffusion Simulation | |
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| Diffusion Systems | |
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| Gettering | |
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| Ion Implantation | |
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| Implantation Technology | |
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| Mathematical Model for Ion Implantation | |
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| Selective Implantation | |
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| Junction Depth and Sheet Resistance | |
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| Channeling, Lattice Damage, and Annealing | |
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| Shallow Implantation | |
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| Source Listing | |
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| Film Deposition | |
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| Evaporation | |
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| Sputtering | |
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| Chemical Vapor Deposition | |
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| Epitaxy | |
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| Further Reading | |
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| Interconnections and Contacts | |
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| Interconnections in Integrated Circuits | |
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| Metal Interconnections and Contact Technology | |
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| Diffused Interconnections | |
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| Polysilicon Interconnections and Buried Contacts | |
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| Silicides and Multilayer-Contact Technology | |
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| The Liftoff Process | |
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| Multilevel Metallization | |
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| Copper Interconnects and Damascene Processes | |
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| Further Reading | |
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| Packaging and Yield | |
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| Testing | |
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| Wafer Thinning and Die Separation | |
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| Die Attachment | |
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| Wire Bonding | |
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| Packages | |
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| Flip-Chip and Tape-Automated-Bonding Processes | |
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| Yield | |
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| Further Reading | |
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| MOS Process Integration | |
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| Basic MOS Device Considerations | |
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| MOS Transistor Layout and Design Rules | |
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| Complementary MOS (CMOS) Technology | |
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| Silicon on Insulator | |
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| Bipolar Process Integration | |
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| The Junction-Isolated Structure | |
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| Current Gain | |
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| Transit Time | |
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| Basewidth | |
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| Breakdown Voltages | |
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| Other Elements in SBC Technology | |
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| Layout Considerations | |
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| Advanced Bipolar Structures | |
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| Other Bipolar Isolation Techniques | |
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| BICMOS | |
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| Processes for Microelectromechanical Systems—MEMS | |
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| Mechanical Properties of Silicon | |
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| Bulk Micromachining | |
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| Silicon Etchants | |
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| Surface Micromachining | |
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| High-Aspect-Ratio Micromachining: The LIGA Molding Process | |
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| Silicon Wafer Bonding | |
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| IC Process Compatibility | |
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| Answers to Selected Problems | |
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| Index | |