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| Preface | |
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| Background and Introduction | |
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| Levels of Abstraction | |
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| From Program to Execution | |
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| A Brief History of Computer Development | |
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| The Intel iAPX Architecture | |
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| Computer Basics | |
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| The Pieces and Parts | |
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| Memory Operation | |
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| The Instruction Fetch and Execute Cycle | |
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| Performance | |
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| SASM--Simple Abstract Language | |
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| Assembly and Compilation | |
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| Variable Declaration | |
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| Arithmetic Operations | |
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| Control Structures | |
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| Communication with the User | |
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| A SASM Program | |
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| Number Systems | |
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| Numbers and Their Representation | |
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| Weighted Positional Notation | |
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| Transformations Between Radices | |
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| Representation of Noninteger Numbers | |
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| Data Representation | |
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| Numbers versus Their Representation | |
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| Representation of Integers | |
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| Characters | |
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| Floating Point Representation | |
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| A Little Extra On Complement Representation | |
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| Arithmetic and Logical Operations | |
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| Logical Operations | |
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| Shift Operations | |
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| Addition and Subtraction | |
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| Multiplication | |
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| Division | |
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| Floating Point Arithmetic | |
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| Hardware versus Software Calculations | |
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| Addition and Subtraction | |
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| Multiplication | |
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| Division | |
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| Advanced Topics | |
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| Data Structures | |
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| Memory as an Array | |
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| Arrays | |
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| Stacks | |
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| Queues | |
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| Using Registers for Efficiency | |
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| Instructions and Efficiency | |
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| Registers | |
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| Load/Store Architectures | |
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| Addressing Modes | |
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| The Pentium Architecture | |
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| Generalities | |
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| Registers | |
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| Memory Model | |
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| Addressing Modes | |
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| Instruction Set | |
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| Code Examples | |
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| Procedures | |
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| Procedure Call and Return Mechanisms | |
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| Dynamic Storage Allocation | |
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| Activation Records | |
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| Parameter Passing | |
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| Saving Registers | |
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| A Pentium Program That Uses Procedures | |
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| The Assembly Process | |
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| Where Assemblers Fit in, and What Assemblers Do | |
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| Machine Code Format and Code Generation | |
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| Linking and Loading | |
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| Input and Output | |
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| Typical I/O Devices | |
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| The Processor--I/O Interface | |
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| Direct Memory Access (DMA) | |
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| Interrupts and Exception Handling | |
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| The Mechanism | |
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| The Role of the Operating System | |
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| The Pentium Exception Mechanism | |
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| Advanced Issues in Exception Handling | |
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| Features for Architectural Performance | |
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| Mimimal Instruction Sets and Choices | |
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| Instruction Level Parallelism | |
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| Memory Hierarchies | |
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| Architecture in Perspective | |
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| What's All This about RISC? | |
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| The Single-Chip Constraint | |
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| The Motorola 68000 Family | |
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| The Cray-1 | |
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| Mips Risc | |
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| Sparc | |
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| Alpha | |
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| Memory Management and Virtual Memory | |
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| Basic Concept and Terms | |
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| Base and Bounds | |
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| Segmentation | |
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| Segmentation on the Pentium | |
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| Paging | |
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| Paging and Segmentation | |
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| Multilevel Paging | |
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| Page and Segment Attributes | |
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| Reserved Word | |