Hardware Design Verification Simulation and Formal Method-Based Approaches

ISBN-10: 0137010923

ISBN-13: 9780137010929

Edition: 2005

Authors: William K. Lam

List price: $183.95
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The Practical, Start-to-Finish Guide to Modern Digital Design Verification As digital logic designs grow larger and more complex, functional verification has become the number one bottleneck in the design process. Reducing verification time is crucial to project success, yet many practicing engineers have had little formal training in verification, and little exposure to the newest solutions.Hardware Design Verificationsystematically presents today's most valuable simulation-based and formal verification techniques, helping test and design engineers choose the best approach for each project, quickly gain confidence in their designs, and move into fabrication far more rapidly. College students will find that coverage of verification principles and common industry practices will help them prepare for jobs as future verification engineers. Author William K. Lam, one of the world's leading experts in design verification, is a recent winner of the Chairman's Award for Innovation, Sun Microsystems'most prestigious technical achievement award. Drawing on his wide-ranging experience, he introduces the foundational principles of verification, presents traditional techniques that have survived the test of time, and introduces emerging techniques for today's most challenging designs. Throughout, Lam emphasizes practical examples rather than mathematical proofs; wherever advanced math is essential, he explains it clearly and accessibly. Coverage includes Simulation-based versus formal verification: advantages, disadvantages, and tradeoffs Coding for verification: functional and timing correctness, syntactical and structure checks, simulation performance, and more Simulator architectures and operations, including event-driven, cycle-based, hybrid, and hardware-based simulators Testbench organization, design, and tools: creating a fast, efficient test environment Test scenarios and assertion: planning, test cases, test generators, commercial and Verilog assertions, and more Ensuring complete coverage, including code, parameters, functions, items, and cross-coverage The verification cycle: failure capture, scope reduction, bug tracking, simulation data dumping, isolation of underlying causes, revision control, regression, release mechanisms, and tape-out criteria An accessible introduction to the mathematics and algorithms of formal verification, from Boolean functions to state-machine equivalence and graph algorithms Decision diagrams, equivalence checking, and symbolic simulation Model checking and symbolic computation Simply put,Hardware Design Verificationwill help you improve and accelerate your entire verification process--from planning through tape-out--so you can get to market faster with higher quality designs.
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Book details

List price: $183.95
Copyright year: 2005
Publisher: Pearson Education, Limited
Publication date: 1/15/2009
Binding: Paperback
Pages: 624
Size: 7.00" wide x 9.10" long x 1.30" tall
Weight: 2.156
Language: English

About the Author
Chapter 1
What Is Design Verification?
The Basic Verification Principle
Verification Methodology
Simulation-Based Verification versus Formal Verification
Limitations of Formal Verification
A Quick Overview of Verilog Scheduling and Execution Semantics
Coding for Verification
Functional Correctness
Timing Correctness
Simulation Performance
Portability and Maintainability
"Synthesizability," "Debugability," and General Tool Compatibility
Cycle-Based Simulation
Hardware Simulation/Emulation
Two-State and Four-State Simulation
Design and Use of a Linter
Simulator Architectures and Operations
The Compilers
The Simulators
Simulator Taxonomy and Comparison
Simulator Operations and Applications
Incremental Compilation
Test Bench Organization and Design
Anatomy of a Test Bench and a Test Environment
Initialization Mechanism
Clock Generation and Synchronization
Stimulus Generation
Response Assessment
Verification Utility
Test Bench-to-Design Interface
Common Practical Techniques and Methodologies
Test Scenarios, Assertions, and Coverage
Hierarchical Verification
Test Plan
Pseudorandom Test Generator
SystemVerilog Assertions
Verification Coverage
Debugging Process and Verification Cycle
Failure Capture, Scope Reduction, and Bug Tracking
Simulation Data Dumping
Isolation of Underlying Causes
Design Update and Maintenance: Revision Control
Regression, Release Mechanism, and Tape-out Criteria
Formal Verification Preliminaries
Sets and Operations
Relation, Partition, Partially Ordered Set, and Lattice
Boolean Functions and Representations
Boolean Functional Operators
Finite-State Automata and Languages
Decision Diagrams, Equivalence Checking, and Symbolic Simulation
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