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| Introduction to Digital Design Methodology | |
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| Design Methodology - An Introduction | |
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| IC Technology Options | |
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| Overview | |
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| Review of Combinational Logic Design | |
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| Combinational Logic and Boolean Algebra | |
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| Theorems for Boolean Algebraic Minimization | |
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| Representation of Combinational Logic | |
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| Simplification of Boolean Expressions | |
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| Glitches and Hazards | |
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| Building Blocks for Logic Design | |
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| Fundamentals of Sequential Logic Design | |
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| Storage Elements | |
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| Flip-Flops | |
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| Busses and Three-State Devices | |
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| Design of Sequential Machines | |
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| State Transition Graphs | |
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| Design Example: BCD to Excess-3 Code Converter | |
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| Serial Line Code Converter for Data Transmission | |
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| State Reduction and Equivalent States | |
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| Introduction to Logic Design with Verilog | |
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| Structural Models of Combinational Logic | |
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| Logic Simulation, Design Verification, and Testbenches | |
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| Propagation Delay | |
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| Truth Table Models of Combinational and Sequential Logic with Verilog | |
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| Logic Design with Behavioral Models of Combinational and Sequential Logic | |
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| Behavioral Modeling | |
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| A Brief Look at Data Types for Behavioral Modeling | |
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| Boolean Equation-Based Behavioral Models of Combinational Logic | |
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| Propagation Delay and Continuous Assignments | |
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| Latches and Level-Sensitive Circuits in Verilog | |
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| Cyclic Behavioral Models of Flip-Flops and Latches | |
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| Cyclic Behavior and Edge Detection | |
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| A Comparison of Styles for Behavioral Modeling | |
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| Behavioral Models of Multiplexers, Encoders, and Decoders | |
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| Dataflow Models of a Linear Feedback Shift Register | |
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| Modeling Digital Machines with Repetitive Algorithms | |
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| Machines with Multi-Cycle Operations | |
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| Design Documentation with Functions and Tasks: Legacy or Lunacy? | |
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| Algorithmic State Machine Charts for Behavioral Modeling | |
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| ASMD Charts | |
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| Behavioral Models of Counters, Shift Registers, and Register Files | |
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| Switch Debounce, Metastability, and Synchronizers for Asynchronous Signals | |
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| Design Example: Keypad Scanner and Encoder | |
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| Synthesis of Combinational and Sequential Logic | |
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| Introduction to Synthesis | |
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| Synthesis of Combinational Logic | |
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| Synthesis of Sequential Logic with Latches | |
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| Synthesis of Three-State Devices and Bus Interfaces | |
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| Synthesis of Sequential Logic with Flip-Flops | |
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| Synthesis of Explicit State Machines | |
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| Registered Logic | |
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| State Encoding | |
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| Synthesis of Implicit State Machines, Registers, and Counters | |
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| Resets | |
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| Synthesis of Gated Clocks and Clock Enables | |
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| Anticipating the Results of Synthesis | |
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| Synthesis of Loops | |
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| Design Traps to Avoid | |
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| Divide and Conquer: Partitioning a Design | |
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| Design and Synthesis of Datapath Controllers | |
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| Partitioned Sequential Machines | |
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| Design Example: Binary Counter | |
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| Design and Synthesis of a Risc Stored Program Machine | |
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| Design Example: Uart | |
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| Programmable Logic and Storage Devices | |
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| Programmable Logic Devices | |
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| Storage Devices | |
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| Programmable Logic Array (PLA) | |
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| Programmable Array Logic (PALTM) | |
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| Programmability of PLDs | |
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| Complex PLDs (CPLDs) | |
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| Altera Max 7000 CPLD | |
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| XILinx XC9500 CPLDs | |
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| Field Programmable Gate Arrays | |
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| Altera Flex 8000 FPGAs | |
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| Altera Flex 10 FPGAs | |
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| Altera Apex FPGAs | |
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| Altera Chip Programmability | |
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| XILinx XC4000 Series FPGA | |
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| XILinx Spartan XL FPGAs | |
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| XILinx Spartan II FPGAs | |
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| XILinx Virtex FPGAs | |
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| Embeddable and Programmable IP Cores for a System on a Chip (SOC) | |
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| Verilog-Based | |