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Preface | |
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Digital Systems and Binary Numbers | |
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Digital Systems | |
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Binary Numbers | |
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Number-Base Conversions | |
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Octal and Hexadecimal Numbers | |
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Complements | |
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Signed Binary Numbers | |
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Binary Codes | |
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Binary Storage and Registers | |
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Binary Logic | |
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Boolean Algebra and Logic Gates | |
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Introduction | |
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Basic Definitions | |
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Axiomatic Definition of Boolean Algebra | |
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Basic Theorems and Properties of Boolean Algebra | |
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Boolean Functions | |
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Canonical and Standard Forms | |
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Other Logic Operations | |
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Digital Logic Gates | |
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Integrated Circuits | |
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Gate-Level Minimization | |
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Introduction | |
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The Map Method | |
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Four-Variable Map | |
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Five-Variable Map | |
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Product-of-Sums Simplification | |
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Don't-Care Conditions | |
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NAND and NOR Implementation | |
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Other Two-Level Implementations | |
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Exclusive-OR Function | |
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Hardware Description Language | |
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Combinational Logic | |
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Introduction | |
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Combinational Circuits | |
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Analysis Procedure | |
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Design Procedure | |
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Binary Adder-Subtractor | |
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Decimal Adder | |
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Binary Multiplier | |
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Magnitude Comparator | |
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Decoders | |
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Encoders | |
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Multiplexers | |
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HDL Models of Combinational Circuits | |
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Synchronous Sequential Logic | |
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Introduction | |
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Sequential Circuits | |
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Storage Elements: Latches | |
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Storage Elements: Flip-Flops | |
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Analysis of Clocked Sequential Circuits | |
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Synthesizable HDL Models of Sequential Circuits | |
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State Reduction and Assignment | |
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Design Procedure | |
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Registers and Counters | |
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Registers | |
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Shift Registers | |
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Ripple Counters | |
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Synchronous Counters | |
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Other Counters | |
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HDL for Registers and Counters | |
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Memory and Programmable Logic | |
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Introduction | |
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Random-Access Memory | |
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Memory Decoding | |
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Error Detection and Correction | |
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Read-Only Memory | |
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Programmable Logic Array | |
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Programmable Array Logic | |
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Sequential Programmable Devices | |
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Design at the Register Transfer Level | |
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Introduction | |
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Register Transfer Level (RTL) Notation | |
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Register Transfer Level in HDL | |
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Algorithmic State Machines (ASMs) | |
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Design Example | |
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HDL Description of Design Example | |
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Sequential Binary Multiplier | |
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Control Logic | |
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HDL Description of Binary Multiplier | |
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Design with Multiplexers | |
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Race-Free Design | |
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Latch-Free Design | |
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Other Language Features | |
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Asynchronous Sequential Logic | |
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Introduction | |
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Analysis Procedure | |
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Circuits with Latches | |
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Design Procedure | |
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Reduction of State and Flow Tables | |
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Race-Free State Assignment | |
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Hazards | |
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Design Example | |
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Digital Integrated Circuits | |
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Introduction | |
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Special Characteristics | |
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Bipolar-Transistor Characteristics | |
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RTL and DTL Circuits | |
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Transistor-Transistor Logic | |
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Emitter-Coupled Logic | |
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Metal-Oxide Semiconductor | |
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Complementary MOS | |
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CMOS Transmission Gate Circuits | |
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Switch-Level Modeling with HDL | |
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Laboratory Experiments with Standard ICs and FPGAs 57 | |
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Introduction to Experiments | |
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Experiment 1: Binary and Decimal Numbers | |
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Experiment 2: Digital Logic Gates | |
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Experiment 3: Simplification of Boolean Functions | |
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Experiment 4: Combinational Circuits | |
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Experiment 5: Code Converters | |
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Experiment 6: Design with Multiplexers | |
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Experiment 7: Adders and Subtractors | |
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Experiment 8: Flip-Flops | |
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Experiment 9: Sequential Circuits | |
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Experiment 10: Counters | |
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Experiment 11: Shift Registers | |
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Experiment 12: Serial Addition | |
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Experiment 13: Memory Unit | |
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Experiment 14: Lamp Handball | |
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Experiment 15: Clock-Pulse Generator | |
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Experiment 16: Parallel Adder and Accumulator | |
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Experiment 17: Binary Multiplier | |
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Experiment 18: Asynchronous Sequential Circuits | |
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Verilog HDL Simulation Experiments and Rapid Prototyping with FPGAs | |
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Standard Graphic Symbols | |
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Rectangular-Shape Symbols | |
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Qualifying Symbols | |
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Dependency Notation | |
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Symbols for Combinational Elements | |
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Symbols for Flip-Flops | |
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Symbols for Registers | |
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Symbols for Counters | |
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Symbol for RAM | |
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Answers to Selected Problems | |
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Index | |