Structured Computer Organization

ISBN-10: 0131485210

ISBN-13: 9780131485211

Edition: 5th 2006 (Revised)

List price: $171.00
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Description:

This book takes a modern structured, layered approach to understanding computer systems. Its highly accessible - and its been thoroughly updated to reflect todays most critical new technologies and the latest developments in computer organization and architecture.Tanenbaumrsquo;s renowned writing style and painstaking research make this one of the most accessible and accurate books available, maintaining the authorrsquo;s popular method of presenting a computer as a series of layers, each one built upon the ones below it, and understandable as a separate entity. A CD-ROM for assembly language programmersnbsp;is available for teachers.For all computer professionals and engineers who need an overview or introduction to computer architecture.
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Book details

List price: $171.00
Edition: 5th
Copyright year: 2006
Publisher: Prentice Hall PTR
Publication date: 6/15/2005
Binding: Mixed Media
Pages: 800
Size: 7.25" wide x 9.25" long x 1.50" tall
Weight: 2.134

Preface
Introduction
Structured Computer Organization
Languages, Levels, and Virtual Machines
Contemporary Multilevel Machines
Evolution of Multilevel Machines
Milestones in Computer Architecture
The Zeroth Generation-Mechanical Computers (1642-1945)
The First Generation-Vacuum Tubes (1945-1955)
The Second Generation-Transistors (1955-1965)
The Third Generation-Integrated Circuits (1965-1980)
The Fourth Generation-Very Large Scale Integration (1980-?)
The Fifth Generation-Invisible Computers
The Computer Zoo
Technological and Economic Forces
The Computer Spectrum
Disposable Computers
Microcontrollers
Game Computers
Personal Computers
Servers
Collections of Workstations
Mainframes
Example Computer Families
Introduction to the Pentium 4
Introduction to the UltraSPARC III
Introduction to the 8051
Metric Units
Outline of This Book
Computer Systems Organization
Processors
CPU Organization
Instruction Execution
RISC versus CISC
Design Principles for Modern Computers
Instruction-Level Parallelism
Processor-Level Parallelism
Primary Memory
Bits
Memory Addresses
Byte Ordering
Error-Correcting Codes
Cache Memory
Memory Packaging and Types
Secondary Memory
Memory Hierarchies
Magnetic Disks
Floppy Disks
IDE Disks
SCSI Disks
RAID
CD-ROMs
CD-Recordables
CD-Rewritables
DVD
Blu-Ray
Input/Output
Buses
Terminals
Mice
Printers
Telecommunications Equipment
Digital Cameras
Character Codes
Summary
The Digital Logic Level
Gates and Boolean Algebra
Gates
Boolean Algebra
Implementation of Boolean Functions
Circuit Equivalence
Basic Digital Logic Circuits
Integrated Circuits
Combinational Circuits
Arithmetic Circuits
Clocks
Memory
Latches
Flip-Flops
Registers
Memory Organization
Memory Chips
RAMs and ROMs
CPU Chips and Buses
CPU Chips
Computer Buses
Bus Width
Bus Clocking
Bus Arbitration
Bus Operations
Example CPU Chips
The Pentium 4
The UltraSPARC III
The 8051
Example Buses
The ISA Bus
The PCI Bus
PCI Express
The Universal Serial Bus
Interfacing
I/O Chips
Address Decoding
Summary
The Microarchitecture Level
An Example Microarchitecture
The Data Path
Microinstructions
Microinstruction Control: The Mic-1
An Example Isa: IJVM
Stacks
The IJVM Memory Model
The IJVM Instruction Set
Compiling Java to IJVM
An Example Implementation
Microinstructions and Notation
Implementation of IJVM Using the Mic-1
Design of the Microarchitecture Level
Speed versus Cost
Reducing the Execution Path Length
A Design with Prefetching: The Mic-2
A Pipelined Design: The Mic-3
A Seven-Stage Pipeline: The Mic-4
Improving Performance
Cache Memory
Branch Prediction
Out-of-Order Execution and Register Renaming
Speculative Execution
Examples of the Microarchitecture Level
The Microarchitecture of the Pentium 4 CPU
The Microarchitecture of the UltraSPARC-III Cu CPU
The Microarchitecture of the 8051 CPU
Comparison of the Pentium, Ultrasparc, and 8051
Summary
The Instruction Set Architecture Level
Overview of the ISA Level
Properties of the ISA Level
Memory Models
Registers
Instructions
Overview of the Pentium 4 ISA Level
Overview of the UltraSPARC III ISA Level
Overview of the 8051 ISA Level
Data Types
Numeric Data Types
Nonnumeric Data Types
Data Types on the Pentium 4
Data Types on the UltraSPARC III
Data Types on the 8051
Instruction Formats
Design Criteria for Instruction Formats
Expanding Opcodes
The Pentium 4 Instruction Formats
The UltraSPARC III Instruction Formats
The 8051 Instruction Formats
Addressing
Addressing Modes
Immediate Addressing
Direct Addressing
Register Addressing
Register Indirect Addressing
Indexed Addressing
Based-Indexed Addressing
Stack Addressing
Addressing Modes for Branch Instructions
Orthogonality of Opcodes and Addressing Modes
The Pentium 4 Addressing Modes
The UltraSPARC III Addressing Modes
The 8051 Addressing Modes
Discussion of Addressing Modes
Instruction Types
Data Movement Instructions
Dyadic Operations
Monadic Operations
Comparisons and Conditional Branches
Procedure Call Instructions
Loop Control
Input/Output
The Pentium 4 Instructions
The UltraSPARC III Instructions
The 8051 Instructions
Comparison of Instruction Sets
Flow of Control
Sequential Flow of Control and Branches
Procedures
Coroutines
Traps
Interrupts
A Detailed Example: The Towers of Hanoi
The Towers of Hanoi in Pentium 4 Assembly Language
The Towers of Hanoi in UltraSPARC III Assembly Language
The IA-64 Architecture and the Itanium 2
The Problem with the Pentium 4
The IA-64 Model: Explicitly Parallel Instruction Computing
Reducing Memory References
Instruction Scheduling
Reducing Conditional Branches: Predication
Speculative Loads
Summary
The Operating System Machine Level
Virtual Memory
Paging
Implementation of Paging
Demand Paging and the Working Set Model
Page Replacement Policy
Page Size and Fragmentation
Segmentation
Implementation of Segmentation
Virtual Memory on the Pentium 4
Virtual Memory on the UltraSPARC III
Virtual Memory and Caching
Virtual I/O Instructions
Files
Implementation of Virtual I/O Instructions
Directory Management Instructions
Virtual Instructions for Parallel Processing
Process Creation
Race Conditions
Process Synchronization Using Semaphores
Example Operating Systems
Introduction
Examples of Virtual Memory
Examples of Virtual I/O
Examples of Process Management
Summary
The Assembly Language Level
Introduction to Assembly Language
What Is an Assembly Language?
Why Use Assembly Language?
Format of an Assembly Language Statement
Pseudoinstructions
Macros
Macro Definition, Call, and Expansion
Macros with Parameters
Advanced Features
Implementation of a Macro Facility in an Assembler
The Assembly Process
Two-Pass Assemblers
Pass One
Pass Two
The Symbol Table
Linking and Loading
Tasks Performed by the Linker
Structure of an Object Module
Binding Time and Dynamic Relocation
Dynamic Linking
Summary
Parallel Computer Architectures
On-Chip Paralellism
Instruction-Level Parallelism
On-Chip Multithreading
Single-Chip Multiprocessors
Coprocessors
Network Processors
Media Processors
Cryptoprocessors
Shared-Memory Multiprocessors
Multiprocessors vs. Multicomputers
Memory Semantics
UMA Symmetric Multiprocessor Architectures
NUMA Multiprocessors
COMA Multiprocessors
Message-Passing Multicomputers
Interconnection Networks
MPPs-Massively Parallel Processors
Cluster Computing
Communication Software for Multicomputers
Scheduling
Application-Level Shared Memory
Performance
Grid Computing
Summary
Reading List and Bibliography
Suggestions for Further Reading
Introduction and General Works
Computer Systems Organization
The Digital Logic Level
The Microarchitecture Level
The Instruction Set Architecture Level
The Operating System Machine Level
The Assembly Language Level
Parallel Computer Architectures
Binary and Floating-Point Numbers
Assembly Language Programming
Alphabetical Bibliography
Binary Numbers
Finte-Precision Numbers
Radix Number Systems
Conversion From One Radix to Another
Negative Binary Numbers
Binary Arithmetic
Floating-Point Numbers
Principles of Floating Point
IEEE Floating-Point Standard 754
Assembly Language Programming
Overview
Assembly Language
A Small Assembly Language Program
The 8088 Processor
The Processor Cycle
The General Registers
Pointer Registers
Memory and Addressing
Memory Organization and Segments
Addressing
The 8088 Instruction Set
Move, Copy and Arithmetic
Logical, Bit and Shift Operations
Loop and Repetitive String Operations
Jump and Call Instructions
Subroutine Calls
System Calls and System Subroutines
Final Remarks on the Instruction Set
The Assembler
Introduction
The ACK-Based Tutorial Assembler as88
Some Differences with Other 8088 Assemblers
The Tracer
Tracer Commands
Getting Started
Examples
Hello World Example
General Registers Example
Call Command and Pointer Registers
Debugging an Array Print Program
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