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Art of Analog Layout

ISBN-10: 0131464108
ISBN-13: 9780131464100
Edition: 2nd 2006 (Revised)
Authors: Alan Hastings
List price: $251.20
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Description: Verbal explanations are favored over mathematical formulas, graphs are kept to a minimum, and line drawings are used in this user-friendly book. Clear guidance and advice are provided for those professionals who lay out analog circuits.Matching of  More...

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Book details

List price: $251.20
Edition: 2nd
Copyright year: 2006
Publisher: Prentice Hall PTR
Publication date: 6/24/2005
Binding: Paperback
Pages: 672
Size: 8.50" wide x 10.25" long x 1.50" tall
Weight: 3.146
Language: English

Verbal explanations are favored over mathematical formulas, graphs are kept to a minimum, and line drawings are used in this user-friendly book. Clear guidance and advice are provided for those professionals who lay out analog circuits.Matching of resistors and capacitors: Includes causes of mismatch, particularly the hydrogen effect and package shift. MOS Transistors: Covers a brief history of floating gate devices, EPROM and EEPROM. Applications of MOS transistors: Expands information on failure mechanisms, including BVdss/Bvdii, SILC, NBTI/PTBI and GIDL and the difference between electrical and electrothermal SOA. Consideration of failure mechanisms as crucial to layout: Integrates further information into many chapters covering various devices. Standard bipolar, polygate CMOS and analog BiCMOS: Covers all three fundamental processes.A valuable reference for professional layout designers.

Preface to the Second Edition
Preface to the First Edition
Acknowledgments
Device Physics
Semiconductors
Generation and Recombination
Extrinsic Semiconductors
Diffusion and Drift
PN Junctions
Depletion Regions
PN Diodes
Schottky Diodes
Zener Diodes
Ohmic Contacts
Bipolar Junction Transistors
Beta
I-V Characteristics
MOS Transistors
Threshold Voltage
I-V Characteristics
JFET Transistors
Summary
Exercises
Semiconductor Fabrication
Silicon Manufacture
Crystal Growth
Wafer Manufacturing
The Crystal Structure of Silicon
Photolithography
Photoresists
Photomasks and Reticles
Patterning
Oxide Growth and Removal
Oxide Growth and Deposition
Oxide Removal
Other Effects of Oxide Growth and Removal
Local Oxidation of Silicon (LOCOS)
Diffusion and Ion Implantation
Diffusion
Other Effects of Diffusion
Ion Implantation
Silicon Deposition and Etching
Epitaxy
Polysilicon Deposition
Dielectric Isolation
Metallization
Deposition and Removal of Aluminum
Refractory Barrier Metal
Silicidation
Interlevel Oxide, Interlevel Nitride, and Protective Overcoat
Copper Metallization
Assembly
Mount and Bond
Packaging
Summary
Exercises
Representative Processes
Standard Bipolar
Essential Features
Fabrication Sequence
Starting Material
N-Buried Layer
Epitaxial Growth
Isolation Diffusion
Base Implant
Emitter Diffusion
Contact
Metallization
Protective Overcoat
Available Devices
NPN Transistors
PNP Transistors
Resistors
Capacitors
Process Extensions
Up-Down Isolation
Double-Level Metal
Schottky Diodes
High-Sheet Resistors
Super-Beta Transistors
Polysilicon-Gate CMOS
Essential Features
Fabrication Sequence
Starting Material
Epitaxial Growth
N-Well Diffusion
Inverse Moat
Channel Stop Implants
LOCOS Processing and Dummy Gate Oxidation
Threshold Adjust
Deep-N+
Polysilicon Deposition and Patterning
Source/Drain Implants
Contacts
Metallization
Protective Overcoat
Available Devices
NMOS Transistors
PMOS Transistors
Substrate PNP Transistors
Resistors
Capacitors
Process Extensions
Double-Level Metal
Shallow Trench Isolation
Silicidation
Lightly Doped Drain (LDD) Transistors
Extended-Drain, High-Voltage Transistors
Analog BiCMOS
Essential Features
Fabrication Sequence
Starting Material
N-Buried Layer
Epitaxial Growth
N-Well Diffusion and
Base Implant
Inverse Moat
Channel Stop Implants
LOCOS Processing and Dummy Gate Oxidation
Threshold Adjust
Polysilicon Deposition and Pattern
Source/Drain Implants
Metallization and Protective Overcoat
Process Comparison
Available Devices
NPN Transistors
PNP Transistors
Resistors
Process Extensions
Advanced Metal Systems
Dielectric Isolation
Summary
Exercises
Failure Mechanisms
Electrical Overstress
Electrostatic Discharge (ESD)
Effects
Preventative Measures
Electromigration
Effects
Preventative Measures
Deep-N+
Dielectric Breakdown
Effects
Preventative Measures
The Antenna Effect
Effects
Preventative Measures
Contamination
Dry Corrosion
Effects
Preventative Measures
Mobile Ion Contamination
Effects
Preventative Measures
Surface Effects
Hot Carrier Injection
Effects
Preventative Measures
Zener Walkout
Effects
Preventative Measures
Avalanche-Induced Beta Degradation
Effects
Preventative Measures
Negative Bias Temperature Instability
Effects
Preventative Measures
Parasitic Channels and Charge Spreading
Effects
Preventative Measures (Standard Bipolar)
Preventative Measures (CMOS and BiCMOS)
Parasitics
Substrate Debiasing
Effects
Preventative Measures
Minority-Carrier Injection
Effects
Preventative Measures (Substrate Injection)
Preventative Measures (Cross-Injection)
Substrate Influence
Effects
Preventative Measures
Summary
Exercises
Resistors
Resistivity and Sheet Resistance
Resistor Layout
Resistor Variability
Process Variation
Temperature Variation
Nonlinearity
Contact Resistance
Resistor Parasitics
Comparison of Available Resistors
Base Resistors
Emitter Resistors
Base Pinch Resistors
High-Sheet Resistors
Epi Pinch Resistors
Metal Resistors
Poly Resistors
NSD and PSD Resistors
N-Well Resistors
Thin-Film Resistors
Adjusting Resistor Values
Tweaking Resistors
Sliding Contacts
Sliding Heads
Trombone Slides
Metal Options
Trimming Resistors
Fuses
Zener Zaps
EPROM Trims
Laser Trims
Summary
Exercises
Capacitors and Inductors
Capacitance
Capacitor Variability
Process Variation
Voltage Modulation and Temperature Variation
Capacitor Parasitics
Comparison of Available Capacitors
Base-Emitter Junction Capacitors
MOS Capacitors
Poly-Poly Capacitors
Stack Capacitors
Lateral Flux Capacitors
High-Permittivity Capacitors
Inductance
Inductor Parasitics
Inductor Construction
Guidelines for Integrating Inductors
Summary
Exercises
Matching of Resistors and Capacitors
Measuring Mismatch
Causes of Mismatch
Random Variation
Capacitors
Resistors
Process Biases
Interconnection Parasitics
Pattern Shift
Etch Rate Variations
Photolithographic Effects
Diffusion Interactions
Hydrogenation
Mechanical Stress and Package Shift
Stress Gradients
Piezoresistivity
Gradients and Centroids
Common-Centroid Layout
Location and Orientation
Temperature Gradients and Thermoelectrics
Thermal Gradients
Thermoelectric Effects
Electrostatic Interactions
Voltage Modulation
Charge Spreading
Dielectric Polarization
Dielectric Relaxation
Rules for Device Matching
Rules for Resistor Matching
Rules for Capacitor Matching
Summary
Exercises
Bipolar Transistors
Topics in Bipolar Transistor Operation
Beta Rolloff
Avalanche Breakdown
Thermal Runaway and Secondary Breakdown
Saturation in NPN Transistors
Saturation in Lateral PNP Transistors
Parasitics of Bipolar Transistors
Standard Bipolar Small-Signal Transistors
The Standard Bipolar NPN Transistor
Construction of Small-Signal NPN Transistors
The Standard Bipolar Substrate PNP Transistor
Construction of Small-Signal Substrate PNP Transistors
The Standard Bipolar Lateral PNP Transistor
Construction of Small-Signal Lateral PNP Transistors
High-Voltage Bipolar Transistors
Super-Beta NPN Transistors
CMOS and BiCMOS Small-Signal Bipolar Transistors
CMOS PNP Transistors
Shallow-Well Transistors
Analog BiCMOS Bipolar Transistors
Fast Bipolar Transistors
Polysilicon-Emitter Transistors
Oxide-Isolated Transistors
Silicon-Germanium Transistors
Summary
Exercises
Applications of Bipolar Transistors
Power Bipolar Transistors
Failure Mechanisms of NPN Power Transistors
Emitter Debiasing
Thermal Runaway and Secondary Breakdown
Kirk Effect
Layout of Power NPN Transistors
The Interdigitated-Emitter Transistor
The Wide-Emitter Narrow-Contact Transistor
The Christmas-Tree Device
The Cruciform-Emitter Transistor
Power Transistor Layout in Analog BiCMOS
Selecting a Power Transistor Layout
Power PNP Transistors
Saturation Detection and Limiting
Matching Bipolar Transistors
Random Variations
Emitter Degeneration
NBL Shadow
Thermal Gradients
Stress Gradients
Filler-Induced Stress
Other Causes of Systomatic Mismatch
Rules for Bipolar Transistor Matching
Rules for Matching Vertical Transistors
Rules for Matching Lateral Transistors
Summary
Exercises
Diodes
Diodes in Standard Bipolar
Diode-Connected Transistors
Zener Diodes
Surface Zener Diodes
Buried Zeners
Schottky Diodes
Power Diodes
Diodes in CMOS and BiCMOS Processes
CMOS Junction Diodes
CMOS and BiCMOS Schottky Diodes
Matching Diodes
Matching PN Junction Diodes
Matching Zener Diodes
Matching Schottky Diodes
Summary
Exercises
Field-Effect Transistors
Topics in MOS Transistor Operation
Modeling the MOS Transistor
Device Transconductance
Threshold Voltage
Parasitics of MOS Transistors
Breakdown Mechanisms
CMOS Latchup
Leakage Mechanisms
Constructing CMOS Transistors
Coding the MOS Transistor
Width and Length
N-Well and P-Well Processes
Channel Stop Implants
Threshold Adjust Implants
Scaling the Transistor
Variant Structures
Serpentine Transistors
Annular Transistors
Backgate Contacts
Floating-Gate Transistors
Principles of Floating-Gate Transistor Operation
Single-Poly Eeprom Memory
The JFET Transistor
Modeling the JFET
JFET Layout
Summary
Exercises
Applications of MOS Transistors
Extended-Voltage Transistors
LDD and DDD Transistors
Extended-Drain Transistors
Extended-Drain NMOS Transistors
Extended-Drain PMOS Transistors
Multiple Gate Oxides
Power MOS Transistors
MOS Safe Operating Area
Electrical SOA
Electrothermal SOA
Rapid Transient Overload
Conventional MOS Power Transistors
The Rectangular Device
The Diagonal Device
Computation of 501 RM
Other Considerations
Nonconventional Structures
DMOS Transistors
The Lateral DMOS Transistor
RESURF Transistors
The DMOS NPN
MOS Transistor Matching
Geometric Effects
Gate Area
Gate Oxide Thickness
Channel Length Modulation
Orientation
Diffusion and Etch Effects
Polysilicon Etch Rate Variations
Diffusion Penetration of Polysilicon
Contacts Over Active Gate
Diffusions Near the Channel
PMOS versus NMOS Transistors
Hydrogenation
Fill Metal and MOS Matching
Thermal and Stress Effects
Oxide Thickness Gradients
Stress Gradients
Thermal Gradients
Common-Centroid Layout of MOS Transistors
Rules for MOS Transistor Matching
Summary
Exercises
Special Topics
Merged Devices
Flawed Device Mergers
Successful Device Mergers
Low-Risk Merged Devices
Medium-Risk Merged Devices
Devising New Merged Devices
The Role of Merged Devices in Analog BiCMOS
Guard Rings
Standard Bipolar Electron Guard Rings
Standard Bipolar Hole Guard Rings
Guard Rings in CMOS and BiCMOS Designs
Single-level Interconnection
Mock Layouts and Stick Diagrams
Techniques for Crossing Leads
Types of Tunnels
Constructing the Padring
Scribe Streets and Alignment Markers
Bondpads,Trimpads, and Testpads
ESD Structures
Zener Clamp
Two-Stage Zener Clamps
Buffered Zener Clamp
Clamp
Clamp
Antiparallel Diode Clamps
Grounded-Gate NMOS Clamps
CDM Clamps
Lateral SCR Clamps
Selecting ESD Structures
Exercises
Assembling the Die
Die Planning
Cell Area Estimation
Resistors
Capacitors
Vertical Bipolar Transistors
Lateral PNP Transistors
MOS Transistors
MOS Power Transistors
Computing Cell Area
Die Area Estimation
Gross Profit Margin
Floorplanning
Top-Level Interconnection
Principles of Channel Routing
Special Routing Techniques
Kelvin Connections
Noisy Signals and Sensitive Signals
Electromigration
Minimizing Stress Effects
Conclusion
Exercises
Appendices
Table of Acronyms Used in the Text
The Miller Indices of a Cubic Crystal
Sample Layout Rules
Mathematical Derivations
Sources for Layout Editor Software
Index

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