Vhdl A Starter's Guide

ISBN-10: 0131457357

ISBN-13: 9780131457355

Edition: 2nd 2005

List price: $116.20 Buy it from $43.03
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Description: For sophomore/junior-level courses in Digital/Logic and Digital Design Laboratory. For schools that wish to introduce VHDL into their undergraduate computer engineering sequence, VHDL is a complex language that is worthy of a dedicated course; yet this is not a practical option in most institutions. This companion text enables instructors to integrate the basic concepts of VHDL into existing courses. It is designed to develop an intuition and a structured way of thinking about VHDL models without spending a great deal of time on advanced language features. Yalamanchili gives students a thorough grounding in the basic concepts and language of VHDL, and encourages them to apply what they have learned using realistic examples. Concepts are followed by examples and tutorials.

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Book details

List price: $116.20
Edition: 2nd
Copyright year: 2005
Publisher: Prentice Hall PTR
Publication date: 12/30/2004
Binding: Paperback
Pages: 256
Size: 6.80" wide x 9.00" long x 0.60" tall
Weight: 1.100
Language: English

Sudhakar Yalamanchili received the BE degree in Electronics from Bangalore University, India in 1978, and the MS and PhD degrees in Electrical and Computer Engineering from the University of Texas at Austin in 1980 and 1984, respectively. He was a Senior and then Principal Research Scientist at the Honeywell Systems and Research Center in Minneapolis from 1984 to 1989 where he was the Principal Investigator for projects in the design and analysis of multiprocessor architectures for embedded applications. Since 1989 he has been on the faculty at the Georgia Institute of Technology where he is currently Professor of Electrical and Computer Engineering. He is the author of the texts VHDL Starter's Guide and Introductory VHDL: From Simulation to Synthesis from Prentice Hall (2000). His current research interests are lay in the intersection of system area networks, configurable computing technologies, and high speed switching and routing. His current projects focus on the development of high-speed switching substrates for supporting data intensive communication. Dr. Yalamanchili is a member of the ACM and Senior Member of the IEEE. He has served as an associate editor for the IEEE Transactions on Parallel and Distributed Systems and IEEE Transactions on Computers and serves in program committees for international conferences in the area of high performance computing systems.

Introduction
What is VHDL?
Digital System Design
The Marketplace
The Role of Hardware Description Languages
Chapter Summary
Modeling Digital Systems
Motivation
Describing Systems
Events, Propagation Delays, and Concurrency
Waveforms and Timing
Signal Values
Shared Signals
Simulating Hardware Descriptions
Chapter Summary
Basic Language Concepts
Signals
Entity-Architecture
Concurrent Statements
Constructing VHDL Models Using CSAs
Understanding Delays
Chapter Summary
Modeling Behaviors
The Process Construct
Programming Constructs
More on Processes
The Wait Statement
Attributes
Generating Clocks and Periodic Waveforms
Using Signals in a Process
Modeling State Machines
Constructing VHDL Models Using Processes
Common Programming Errors
Chapter Summary
Modeling Structure
Describing Structure
Constructing Structural VHDL Models
Hierarchy, Abstraction, and Accuracy
Generics
The Generate Statement
Configurations
Common Programming Errors
Chapter Summary
Subprograms, Packages, and Libraries
Essentials of Functions
Essentials of Procedures
Subprogram and Operator Overloading
Essentials of Packages
Essentials of Libraries
Chapter Summary
Basic Input/Output
Basic Input/Output Operations
The Package TEXTIO
Testbenches in VHDL
ASSERT Statement
A Testbench Template
Chapter Summary
Simulation Mechanics
Terminology and Directory Structure
Simulation Steps
Chapter Summary
Identifiers, Data Types, and Operators
Identifiers
Data Objects
Data Types
Operators
Chapter Summary
References
Active-HDL Tutorial
Using Active VHDL
Miscellaneous Features
Chapter Summary
Standard VHDL Packages
Package STANDARD
Package TEXTIO
The Standard Logic Package
Other Useful Packages
Starting Program Template
Construct Schematic
Construct The Behavioral Model
Index
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