Introductory VHDL From Simulation to Synthesis

ISBN-10: 0130809829

ISBN-13: 9780130809827

Edition: 2001

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Description:

For courses in Hardware Description Languages, Digital Design Laboratory, Digital Design, and Advanced Digital Design. This text focuses on presenting the basic features of the VHDL language in the context of its use for both simulation and synthesis. Basic language concepts are motivated by familiarity with digital logic circuits with simulation and synthesis presented as complementary design processes. Field programmable gate arrays are used as the medium for synthesis laboratory exercises, and tutorials are provided for the use of the new integrated design environments from Xilinxwhich is available with the text.
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Book details

List price: $237.00
Copyright year: 2001
Publisher: Prentice Hall PTR
Publication date: 7/13/2000
Binding: Paperback
Pages: 320
Size: 7.00" wide x 9.10" long x 1.00" tall
Weight: 2.090
Language: English

Sudhakar Yalamanchili received the BE degree in Electronics from Bangalore University, India in 1978, and the MS and PhD degrees in Electrical and Computer Engineering from the University of Texas at Austin in 1980 and 1984, respectively. He was a Senior and then Principal Research Scientist at the Honeywell Systems and Research Center in Minneapolis from 1984 to 1989 where he was the Principal Investigator for projects in the design and analysis of multiprocessor architectures for embedded applications. Since 1989 he has been on the faculty at the Georgia Institute of Technology where he is currently Professor of Electrical and Computer Engineering. He is the author of the texts VHDL Starter's Guide and Introductory VHDL: From Simulation to Synthesis from Prentice Hall (2000). His current research interests are lay in the intersection of system area networks, configurable computing technologies, and high speed switching and routing. His current projects focus on the development of high-speed switching substrates for supporting data intensive communication. Dr. Yalamanchili is a member of the ACM and Senior Member of the IEEE. He has served as an associate editor for the IEEE Transactions on Parallel and Distributed Systems and IEEE Transactions on Computers and serves in program committees for international conferences in the area of high performance computing systems.

Preface
Introduction
What is VHDL?
Digital System Design
The Marketplace
The Role of Hardware Description Languages
Chapter Summary
Modeling Digital Systems
Motivation
Describing Systems
Events, Propagation Delays, and Concurrency
Waveforms and Timing
Signal Values
Shared Signals
Chapter Summary
Simulation vs. Synthesis
The Simulation Model
A Discrete Event Simulation Model
Accuracy vs. Simulation Speed
The Synthesis Model
Hardware Inference
Target Primitives
Field Programmable Gate Arrays (FPGAs)
Implementation of CLBs
Implementation of the Switch Matrix
Implementation of the IOB
Configuration
FPGA Design Flow
Chapter Summary
Basic Language Concepts: Simulation
Signals
Entity--Architecture
Concurrent Statements
Simple CSA
Implementation of Signals
Resolved Signals
Conditional Signal Assignment
Selected Signal Assignment Statement
Constructing VHDL Models Using CSAs
Understanding Delays
The Inertial Delay Model
The Transport Delay Model
Delta Delays
Chapter Summary
Basic Language Concepts: Synthesis
A Language Directed View of Synthesis
Inference from Declarations
Inference From Simple CSA Statements
Inference From Conditional Signal Assignment Statements
Inference from Selected Signal Assignment Statements
Simulation Behavior vs. Synthesis Behavior
Synthesis Hints
Summary
Exercises
Modeling Behavior: Simulation
The Process Construct
Programming Constructs
If-Then-Else and If-Then-Elsif Statements
Case Statement
Loop Statements
More on Processes
The Wait Statement
Attributes
Function Attributes
Value Attributes
Signal Attributes
Range Attribute
Type Attributes
Generating Clocks and Periodic Waveforms
Using Signals in a Process
Modeling State Machines
Constructing VHDL Models Using Processes
Common Programming Errors
Common Syntax Errors
Common Run-Time Errors
Chapter Summary
Modeling Behavior: Synthesis
A Language Directed View of Synthesis
Inference From Within Processes
Simple Assignment Statements
If-Then-Else and If-Then-Elsif Statements
Case Statement
Loop Statements
Miscellaneous Issues
Inference Using Signals vs. Variables
Latch vs. Flip-Flop Inference
The Wait Statement
Synthesis of State Machines
Simulation vs. Synthesis
Synthesis Hints
Chapter Summary
Modeling Structure
Describing Structure
Constructing Structural VHDL Models
Hierarchy, Abstraction, and Accuracy
Generics
Specifying Generic Values
Some Rules about Using Generics
Component Instantiation and Synthesis
The Generate Statement
Configurations
Default Binding Rules
Configuration Specification
Configuration Declaration
Common Programming Errors
Chapter Summary
Sub-Programs, Packages, and Libraries
Essentials of Functions
Type Conversion Functions
Resolution Functions
Synthesis Considerations
Essentials of Procedures
Using Procedures
Concurrent and Sequential Procedure Calls
Synthesis Considerations
Sub-Program and Operator Overloading
Essentials of Packages
Essentials of Libraries
Chapter Summary
Basic I/O
Basic I/O Operations
File Declarations
Opening and Closing Files
Reading and Writing Files
VHDL 1987 I/O
The Package TEXTIO
Testbenches in VHDL
ASSERT Statement
A Testbench Template
Chapter Summary
Programming Mechanics
Terminology and Directory Structure
Simulation Mechanics
Analyzing VHDL Programs
Elaboration of VHDL Programs
Initialization of VHDL Programs
Simulation Of VHDL Programs
Synthesis Mechanics
Analysis
Synthesis of a Design
Mapping a Design
Place and Route
Bit Generation
Programming
Chapter Summary
Identifiers, Data Types, and Operators
Identifiers
Data Objects
Data Types
The Standard Data Types
Enumerated Types
Array Types
Physical Types
Operators
Chapter Summary
Synthesis Hints: Beginner's Reference
Some Useful Hints and Observations
Initialization
Inferring Storage
Optimizations
Potpourri
Consistency with Pre-Synthesis Functional Simulation
Suggestions for Managing Models and Course Projects
VHDL 1987 vs. VHDL 1993
Active-HDL Tutorial
Active VHDL
Miscellaneous Features
Chapter Summary
Xilinx Foundation Express Tutorial
Tutorial
Chapter Summary
Synopsys FPGA Express Tutorial
Using FPGA Express
Chapter Summary
Standard VHDL Packages
Package STANDARD
Package TEXTIO
The Standard Logic Package
Other Useful Packages
A Starting Program Template
A Simulation Template
Construct_Schematic
Construct_Behavioral_Model
A Synthesis Template
References
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