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| Preface | |
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| Binary Systems | |
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| Digital Computers and Digital Systems | |
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| Binary Numbers | |
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| Number Base Conversions | |
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| Octal and Hexadecimal Numbers | |
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| Complements | |
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| Signed Binary Numbers | |
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| Binary Codes | |
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| Binary Storage and Registers | |
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| Binary Logic | |
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| References | |
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| Problems | |
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| Boolean Algebra and Logic Gates | |
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| Basic Definitions | |
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| Axiomatic Definition of Boolean Algebra | |
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| Basic Theorems and Properties of Boolean Algebra | |
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| Boolean Functions | |
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| Canonical and Standard Forms | |
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| Other Logic Operations | |
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| Digital Logic Gates | |
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| Integrated Circuits | |
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| References | |
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| Problems | |
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| Simplification of Boolean Functions | |
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| The Map Method | |
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| Two- and Three-Variable Maps | |
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| Four-Variable Map | |
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| Five-Variable Map | |
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| Product of Sums Simplification | |
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| NAND and NOR Implementation | |
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| Other Two-Level Implementations | |
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| Don't-Care Conditions | |
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| The Tabulation Method | |
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| Determination of Prime Implicants | |
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| Selection of Prime Implicants | |
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| Concluding Remarks | |
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| References | |
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| Problems | |
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| Combinational Logic | |
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| Introduction | |
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| Design Procedure | |
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| Adders | |
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| Subtractors | |
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| Code Conversion | |
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| Analysis Procedure | |
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| Multilevel NAND Circuits | |
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| Multilevel NOR Circuits | |
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| Exclusive-OR Functions | |
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| References | |
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| Problems | |
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| MSI and PLD Components | |
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| Introduction | |
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| Binary Adder and Subtractor | |
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| Decimal Adder | |
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| Magnitude Comparator | |
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| Decoders and Encoders | |
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| Multiplexers | |
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| Read-Only Memory (ROM) | |
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| Programmable Logic Array (PLA) | |
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| Programmable Array Logic (PAL) | |
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| References | |
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| Problems | |
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| Synchronous Sequential Logic | |
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| Introduction | |
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| Flip-Flops | |
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| Triggering of Flip-Flops | |
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| Analysis of Clocked Sequential Circuits | |
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| State Reduction and Assignment | |
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| Flip-Flop Excitation Tables | |
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| Design Procedure | |
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| Design of Counters | |
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| References | |
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| Problems | |
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| Registers, Counters, and the Memory Unit | |
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| Introduction | |
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| Registers | |
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| Shift Registers | |
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| Ripple Counters | |
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| Synchronous Counters | |
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| Timing Sequences | |
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| Random-Access Memory (RAM) | |
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| Memory Decoding | |
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| Error-Correcting Codes | |
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| References | |
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| Problems | |
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| Algorithmic State Machines (ASM) | |
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| Introduction | |
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| ASM Chart | |
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| Timing Considerations | |
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| Control Implementation | |
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| Design with Multiplexers | |
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| PLA Control | |
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| References | |
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| Problems | |
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| Asynchronous Sequential Logic | |
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| Introduction | |
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| Analysis Procedure | |
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| Circuits with Latches | |
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| Design Procedure | |
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| Reduction of State and Flow Tables | |
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| Race-Free State Assignment | |
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| Hazards | |
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| Design Example | |
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| References | |
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| Problems | |
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| Digital Integrated Circuits | |
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| Introduction | |
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| Special Characteristics | |
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| Bipolar-Transistor Characteristics | |
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| RTL and DTL Circuits | |
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| Transistor-Transistor Logic (TTL) | |
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| Emmitter-Coupled Logic (ECL) | |
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| Metal-Oxide Semiconductor (MOS) | |
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| Complementary MOS (CMOS) | |
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| CMOS Transmission Gate Circuits | |
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| References | |
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| Problems | |
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| Laboratory Experiments | |
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| Introduction to Experiments | |
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| Binary and Decimal Numbers | |
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| Digital Logic Gates | |
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| Simplification of Boolean Functions | |
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| Combinational Circuits | |
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| Code Converters | |
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| Design with Multiplexers | |
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| Adders and Subtractors | |
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| Flip-Flops | |
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| Sequential Circuits | |
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| Counters | |
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| Shift Registers | |
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| Serial Addition | |
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| Memory Unit | |
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| Lamp Handball | |
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| Clock-Pulse Generator | |
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| Parallel Adder | |
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| Binary Multiplier | |
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| Asynchronous Sequential Circuits | |
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| Standard Graphic Symbols | |
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| Rectangular-Shape Symbols | |
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| Qualifying Symbols | |
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| Dependency Notation | |
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| Symbols for Combinational Elements | |
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| Symbols for Flip-Flops | |
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| Symbols for Registers | |
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| Symbols for Counters | |
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| Symbol for RAM | |
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| References | |
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| Problems | |
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| Answers to Selected Problems | |
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| Index | |