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(NOTE:Each chapter concludes with a Summary and Exercises.) | |
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About the Author | |
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Foreword | |
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Preface | |
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Acknowledgments | |
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Basic Verilog Topics | |
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Overview of Digital Design with Verilog HDL. Evolution of Computer-Aided Digital Design. Emergence of HDLs. Typical Design Flow. Importance of HDLs. Popularity of Verilog HDL. Trends in HDLs | |
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Hierarchical Modeling Concepts | |
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Design Methodologies. 4-bit Ripple Carry Counter. Modules. Instances. Components of a Simulation. Example | |
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Basic Concepts | |
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Lexical Conventions. Data Types. System Tasks and Compiler Directives | |
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Modules and Ports | |
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Modules. Ports. Hierarchical Names | |
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Gate-Level Modeling | |
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Gate Types. Gate Delays | |
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Dataflow Modeling | |
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Continuous Assignments. Delays. Expressions, Operators, and Operands. Operator Types. Examples | |
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Behavioral Modeling | |
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Structured Procedures. Procedural Assignments. Timing Controls. Conditional Statements. Multiway Branching. Loops. Sequential and Parallel Blocks. Generate Blocks. Examples | |
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Tasks and Functions | |
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Difference between Tasks and Functions. Tasks. Functions | |
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Useful Modeling Techniques | |
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Procedural Continuous Assignments. Overriding Parameters. Conditional Compilation and Execution. Time Scales. Useful System Tasks | |
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Advanced Verilog Topics | |
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Timing and Delays | |
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Types of Delay Models. Path Delay Modeling. Timing Checks. Delay Back-Annotation | |
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Switch Level Modeling | |
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Switching-Modeling Elements. Examples | |
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User-Defined Primitives | |
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UDP basics. Combinational UDPs. Sequential UDPs. UDP Table Shorthand Symbols. Guidelines for UDP Design | |
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Programming Language Interface | |
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Uses of PLI. Linking and Invocation of PLI Tasks. Internal Data Representation. PLI Library Routines | |
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Logic Synthesis with Verilog HDL. What Is Logic Synthesis? Impact of Logic Synthesis. Verilog HDL Synthesis. Synthesis Design Flow. Verification of the Gate-Level Netlist. Modeling Tips for Logic Synthesis. Example of Sequential Circuit Synthesis | |
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Advanced Verification Techniques | |
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Traditional Verification Flow. Assertion Checking. Formal Verification | |
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Appendices | |
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Strength Modeling and Advanced Net Definitions Strength Levels | |
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Signal Contention. Advanced Net Types | |
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List of PLI Routines Conventions | |
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Access Routines. Utility (tf_) Routines | |
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List of Keywords, System Tasks and Compiler Directives Keywords | |
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System Tasks and Functions. Compiler Directives | |
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Formal Syntax Definition Source Text. Declarations | |
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Primitive Instances. Module and Generated Instantiation | |
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UDP Declaration and Instantiation. Behavioral Statements | |
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Specify Section. Expressions. General | |
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Verilog Tidbits | |
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