VHDL Coding and Logic Synthesis with Synopsys

Name: VHDL Coding and Logic Synthesis with Synopsys
Availability: OutOfStock
ISBN: 9780124406513

ISBN-10: 0124406513

ISBN-13: 9780124406513

Edition: 2000

Authors: Weng Fook Lee

List price: $89.95

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Description:

Weng Fook Lee explains and explores the design of integrated circuits. The use of Synopsys as a tool is highlighted as a popular method of designing integrated circuits for higher speeds covering smaller surface areas.

Book details

List price: $89.95
Copyright year: 2000
Publisher: Elsevier Science & Technology Books
Publication date: 8/22/2000
Binding: Hardcover
Pages: 392
Size: 7.52" wide x 9.25" long x 0.50" tall
Weight: 2.244
Language: English



List of Figures


List of Tables


List of Examples


Preface


Acknowledgment


Trademarks


VHDL Coding


Introduction


Conventional Design--Schematic Capture


Hardware Description Language


VHDL Design Structure


Component Instantiation Within a VHDL Design Structure


Structural, Behavioral, and Synthesizable VHDL Design Structure


Structural VHDL


Behavioral VHDL


RTL Code


Usage of Library Declarations in VHDL Design Structure


VHDL Simulation and Synthesis Flow


Synthesizable Code for Basic Logic Components


AND Logic


OR Logic


NOT Logic


NAND Logic


NOR Logic


Tristate Buffer Logic


Complex Logic Gate


Latch


Avoiding Latches In Your Code


Flip-Flop


Decoder


Encoder


Multiplexer


Priority Encoder


Memory Cell


Adder


Component Inference


Signal Versus Variable


Variable


Signal


When to Use Signal and When to Use Variable


Usage of Loopback Signal


Examples of Complex Synthesizable Code


Shifter


Counter


Memory Module


Car Traffic Controller


Pipeline Microcontroller Synthesizable Design


Instruction Set Definition


Architectural Definition


Pipeline Definition


Microarchitecture Definition for the Pipeline Microcontroller


Predecode Block


Decode Block


Register File Block


Execute Block


Fullchip Microcontroller


Logic Synthesis with Synopsys


Timing Considerations in Design


Setup Timing Violation


Hold Timing Violation


Setup/Hold Timing Considerations in Synthesis


Microarchitectural Tweaks for Fixing Setup Time Violations


Logic Duplication to Generate Independent Paths


Logic Duplication Prior to Selection of Later Arriving Signal


Balancing of Logic between Flip-Flops


Priority Decoding Versus Multiplex Decoding


Microarchitectural Tweaks for Fixing Hold Time Violations


Asynchronous/False Paths


Multicycle Paths


VHDL Synthesis with Timing Constraints


Introduction to Design Compiler


Using Design Compiler for Synthesis


Performance Tweaks


Compilation With 'map_effort high' Option


Group Critical Paths Together and Give Them a Weight Factor


Logical Flattening of a Design


Characterizing Submodules


Register Balancing


Usage of FSM Compiler to Optimize Finite State Machine


Choosing High-Speed Implementation for High-level Functional Module


Balancing of Logic Trees with Heavy Loading


Area Optimization in Synthesis Tweaks


Do Not Use Combinational Logic as Individual Blocks


Do Not Use Glue Logic between Modules


set_max_area Attribute


Fixing Hold-Time Violations in Synopsys


Misc Synthesis Commands Generally Used


Top-Down and Bottoms-Up Compilation


GTECH Instantiation


DesignWare Library


Creating Your Own Design Ware Library


Testability Issues in Synthesis


Multiplexed Flip-Flop Scan Style


Using Synopsys Test Compiler for Scan Insertion


FPGA Synthesis


Synthesis Links to Layout


Forward-Annotation


Wireload Models


Floorplanning a Design


Post Layout Optimization


Design Guideline to Follow for Efficient Synthesis


Appendix A (STD_LOGIC_1164 Library)


Appendix B (Shifter Synthesis Results)


Appendix C (Counter Synthesis Results)


Appendix D (Pipeline Microcontroller Synthesis Results--Top-Down Compilation)


Appendix E (EDIF File of Synthesized Microcontroller Example from Chapter 6)


Appendix F (SDF File from Synthesized Microcontroller Example of Chapter 6)


Glossary


Bibliography


Index