Computer Organization and Design The Hardware/Software Interface

ISBN-10: 0124077269
ISBN-13: 9780124077263
Edition: 5th 2013
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Description: The 5th edition of Computer Organization and Design moves forward into the post-PC era with new examples, exercises, and material highlighting the emergence of mobile computing and the cloud. This generational change is emphasized and explored with  More...

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Book details

List price: $89.95
Edition: 5th
Copyright year: 2013
Publisher: Elsevier Science & Technology Books
Publication date: 9/26/2013
Binding: Paperback
Pages: 800
Size: 7.50" wide x 9.25" long x 1.00" tall
Weight: 2.794
Language: English

The 5th edition of Computer Organization and Design moves forward into the post-PC era with new examples, exercises, and material highlighting the emergence of mobile computing and the cloud. This generational change is emphasized and explored with updated content featuring tablet computers, cloud infrastructure, and the ARM (mobile computing devices) and x86 (cloud computing) architectures. Because an understanding of modern hardware is essential to achieving good performance and energy efficiency, this edition adds a new concrete example, "Going Faster," used throughout the text to demonstrate extremely effective optimization techniques. Also new to this edition is discussion of the "Eight Great Ideas" of computer architecture. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, computer arithmetic, pipelining, memory hierarchies and I/O. Instructors looking for 4th Edition teaching materials should e-mail textbook@elsevier.com. Optimization techniques featured throughout the text Covers parallelism in depth with examples and content highlighting parallel hardware and software topics Features the Intel Core i7, ARM Cortex-A8 and NVIDIA Fermi GPU as real-world examples throughout the book Online companion website provides links to simulators and compilers along with tutorials for using them, as well as additional advanced content, appendices, glossary, references, "Historical Perspectives," and recommended reading

David A. Patterson was the first in his family to graduate from college (1969 A.B UCLA), and he enjoyed it so much that he didn't stop until a PhD, (1976 UCLA). After 4 years developing a wafer-scale computer at Hughes Aircraft, he joined U.C. Berkeley in 1977. He spent 1979 at DEC working on the VAX minicomputer. He and colleagues later developed the Reduced Instruction Set Computer (RISC). By joining forces with IBM's 801 and Stanford's MIPS projects, RISC became widespread. In 1984 Sun Microsystems recruited him to start the SPARC architecture. In 1987, Patterson and colleagues wondered if tried building dependable storage systems from the new PC disks. This led to the popular Redundant Array of Inexpensive Disks (RAID). He spent 1989 working on the CM-5 supercomputer. Patterson and colleagues later tried building a supercomputer using standard desktop computers and switches. The resulting Network of Workstations (NOW) project led to cluster technology used by many startups. He is now working on the Recovery Oriented Computing (ROC) project. In the past, he served as Chair of Berkeley's CS Division, Chair and CRA. He is currently serving on the IT advisory committee to the U.S. President and has just been elected President of the ACM. All this resulted in 150 papers, 5 books, and the following honors, some shared with friends: election to the National Academy of Engineering; from the University of California: Outstanding Alumnus Award (UCLA Computer Science Department), McEntyre Award for Excellence in Teaching (Berkeley Computer Science), Distinguished Teaching Award (Berkeley); from ACM: fellow, SIGMOD Test of Time Award, Karlstrom Outstanding Educator Award; from IEEE: fellow, Johnson Information Storage Award, Undergraduate Teaching Award, Mulligan Education Medal, and von Neumann Medal.

John L. Hennessy is the president of Stanford University, where he has been a member of the faculty since 1977 in the departments of electrical engineering and computer science. Hennessy is a fellow of the IEEE and the ACM, a member of the National Academy of Engineering, the National Academy of Science, the American Academy of Arts and Sciences, and the Spanish Royal Academy of Engineering. He received the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and shared the John von Neumann award in 2000 with David Patterson. After completing the project in 1984, he took a one-year leave from the university to co-found MIPS Computer Systems, which developed one of the first commercial RISC microprocessors. After being acquired by Silicon Graphics in 1991, MIPS Technologies became an independent company in 1998, focusing on microprocessors for the embedded marketplace. As of 2004, over 300 million MIPS microprocessors have been shipped in devices ranging from video games and palmtop computers to laser printers and network switches. Hennessy's more recent research at Stanford focuses on the area of designing and exploiting multiprocessors. He helped lead the design of the DASH multiprocessor architecture, the first distributed shared-memory multiprocessors supporting cache coherency, and the basis for several commercial multiprocessor designs, including the Silicon Graphics Origin multiprocessors. Since becoming president of Stanford, revising and updating this text and the more advanced Computer Architecture: A Quantitative Approach has become a primary form of recreation and relaxation.

Preface
Computer Abstractions and Technology
Introduction
Eight Great Ideas in Computer Architecture
Below Your Program
Under the Covers
Technologies for Building Processors and Memory
Performance
The Power Wall
The Sea Change: The Switch from Uniprocessors to Multiprocessors
Real Stuff: Benchmarking the Intel Core i7
Fallacies and Pitfalls
Concluding Remarks
Historical Perspective and Further Reading
Exercises
Instructions: Language of the Computer
Introduction
Operations of the Computer Hardware
Operands of the Computer Hardware
Signed and Unsigned Numbers
Representing Instructions in the Computer
Logical Operations
Instructions for Making Decisions
Supporting Procedures in Computer Hardware
Communicating with People
MIPS Addressing for 32-Bit Immediates and Addresses
Parallelism and Instructions: Synchronization
Translating and Starting a Program
AC Sort Example to Put It All Together
Arrays versus Pointers
Advanced Material: Compiling C and Interpreting Java
Real Stuff: ARMv7 (32-bit) Instructions
Real Stuff: x86 Instructions
Real Stuff: ARMv8 (64-bit) Instructions
Fallacies and Pitfalls
Concluding Remarks
Historical Perspective and Further Reading
Exercises
Arithmetic for Computers
Introduction
Addition and Subtraction
Multiplication
Division
Floating Point
Parallelism and Computer Arithmetic: Subword Parallelism
Real Stuff: Streaming SIMD Extensions and Advanced Vector Extensions in x86
Going Faster: Subword Parallelism and Matrix Multiply
Fallacies and Pitfalls
Concluding Remarks
Historical Perspective and Further Reading
Exercises
The Processor
Introduction
Logic Design Conventions
Building a Datapath
A Simple Implementation Scheme
An Overview of Pipelining
Pipelined Datapath and Control
Data Hazards: Forwarding versus Stalling
Control Hazards
Exceptions
Parallelism via Instructions
Real Stuff: The ARM Cortex-A8 and Intel Core i7 Pipelines
Going Faster: Instruction-Level Parallelism and Matrix Multiply
Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations
Fallacies and Pitfalls
Concluding Remarks
Historical Perspective and Further Reading
Exercises
Large and Fast: Exploiting Memory Hierarchy
Introduction
Memory Technologies
The Basics of Caches
Measuring and Improving Cache Performance
Dependable Memory Hierarchy
Virtual Machines
Virtual Memory
A Common Framework for Memory Hierarchy
Using a Finite-State Machine to Control a Simple Cache
Parallelism and Memory Hierarchies: Cache Coherence
Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks
Advanced Material: Implementing Cache Controllers
Real Stuff: The ARM Cortex-A8 and Intel Core i7 Memory Hierarchies
Going Faster: Cache Blocking and Matrix Multiply
Fallacies and Pitfalls
Concluding Remarks
Historical Perspective and Further Reading
Exercises
Parallel Processors from Client to Cloud
Introduction
The Difficulty of Creating Parallel Processing Programs
SISD.MLMD, SIMD, SPMD, and Vector
Hardware Multithreading
Multicore and Other Shared Memory Multiprocessors
Introduction to Graphics Processing Units
Clusters, Warehouse Scale Computers, and Other Message-Passing Multiprocessors
Introduction to Multiprocessor Network Topologies
Communicating to the Outside World: Cluster Networking
Multiprocessor Benchmarks and Performance Models
Real Stuff: Benchmarking Intel Core 17 versus NVIDIA Tesla GPU
Going Faster: Multiple Processors and Matrix Multiply
Fallacies and Pitfalls
Concluding Remarks
Historical Perspective and Further Reading
Exercises
Appendices
Assemblers, Linkers, and the SPIM Simulator
Introduction
Assemblers
Linkers
Loading
Memory Usage
Procedure Call Convention
Exceptions and Interrupts
Input and Output
SPIM
MIPS R2000 Assembly Language
Concluding Remarks
Exercises
The Basics of Logic Design
Introduction
Gates, Truth Tables, and Logic Equations
Combinational Logic
Using a Hardware Description Language
Constructing a Basic Arithmetic Logic Unit
Faster Addition: Carry Lookahead
Clocks
Memory Elements: Flip-Flops, Latches, and Registers
Memory Elements: SRAMs and DRAMs
Finite-State Machines
Timing Methodologies
Field Programmable Devices
Concluding Remarks
Exercises
Index
Graphics and Computing GPUs
Introduction
GPU System Architectures
Programming GPUs
Multithreaded Multiprocessor Architecture
Parallel Memory System
Floating Point Arithmetic
Real Stuff: The NVIDIA GeForce 8800
Real Stuff: Mapping Applications to GPUs
Fallacies and Pitfalls
Concluding Remarks
Historical Perspective and Further Reading
Mapping Control to Hardware
Introduction
Implementing Combinational Control Units
Implementing Finite-State Machine Control
Implementing the Next-State Function with a Sequencer
Translating a Microprogram to Hardware
Concluding Remarks
Exercises
A Survey of RISC Architectures for Desktop, Server, and Embedded Computers
Introduction
Addressing Modes and Instruction Formats
Instructions: The MIPS Core Subset
Instructions: Multimedia Extensions of the Desktop/Server RISCs
Instructions: Digital Signal-Processing Extensions of the Embedded RISCs
Instructions: Common Extensions to MIPS Core
Instructions Unique to MIPS-64
Instructions Unique to Alpha
Instructions Unique to SPARC v9
Instructions Unique to PowerPC
instructions Unique to PA-RISC 2.0
Instructions Unique to ARM
Instructions Unique to Thumb
Instructions Unique to SuperH
Instructions Unique to M32R
Instructions Unique to MIPS-16
Concluding Remarks
Glossary
Further Reading

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