See MIPS Run

ISBN-10: 0120884216
ISBN-13: 9780120884216
Edition: 2nd 2007
Authors: Dominic Sweetman
List price: $84.95
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Description: This second edition is not only a thorough update of the first edition, it is also a marriage of the best-known RISC architecture--MIPS--with the best-known open-source OS--Linux. The first part of the book begins with MIPS design principles and  More...

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Book details

List price: $84.95
Edition: 2nd
Copyright year: 2007
Publisher: Elsevier Science & Technology Books
Publication date: 10/17/2006
Binding: Paperback
Pages: 512
Size: 7.25" wide x 9.00" long x 1.25" tall
Weight: 2.574
Language: English

This second edition is not only a thorough update of the first edition, it is also a marriage of the best-known RISC architecture--MIPS--with the best-known open-source OS--Linux. The first part of the book begins with MIPS design principles and then describes the MIPS instruction set and programmers??? resources. It uses the MIPS32 standard as a baseline (the 1st edition used the R3000) from which to compare all other versions of the architecture and assumes that MIPS64 is the main option. The second part is a significant change from the first edition. It provides concrete examples of operating system low level code, by using Linux as the example operating system. It describes how Linux is built on the foundations the MIPS hardware provides and summarizes the Linux application environment, describing the libraries, kernel device-drivers and CPU-specific code. It then digs deep into application code and library support, protection and memory management, interrupts in the Linux kernel and multiprocessor Linux. Sweetman has revised his best-selling MIPS bible for MIPS programmers, embedded systems designers, developers and programmers, who need an in-depth understanding of the MIPS architecture and specific guidance for writing software for MIPS-based systems, which are increasingly Linux-based. * Completely new material offers the best explanation available on how Linux runs on real hardware. * Provides a complete, updated and easy-to-use guide to the MIPS instruction set using the MIPS32 standard as the baseline architecture with the MIPS64 as the main option. * Retains the same engaging writing style that made the first edition so readable, reflecting the authors 20+years experience in designing systems based on the MIPS architecture.

Foreword
Preface
Style and Limits
Conventions
Acknowledgments
RISCs and MIPS Architectures
Pipelines
What Makes a Pipeline Inefficient?
The Pipeline and Caching
The MIPS Five-Stage Pipeline
RISC and CISC
Great MIPS Chips of the Past and Present
R2000 to R3000 Processors
The R6000 Processor: A Diversion
The First CPU Cores
The R4000 Processor: A Revolution
The Rise and Fall of the ACE Consortium
SGI Acquires MIPS
QED: Fast MIPS Processors for Embedded Systems
The R10000 Processor and its Successors
MIPS Processors in Consumer Electronics
MIPS in Network Routers and Laser Printers
MIPS Processors in Modern Times
The Rebirth of MIPS Technologies
The Present Day
MIPS Compared with CISC Architectures
Constraints on MIPS Instructions
Addressing and Memory Accesses
Features You Won't Find
Programmer-Visible Pipeline Effects
MIPS Architecture
A Flavor of MIPS Assembly Language
Registers
Conventional Names and Uses of General-Purpose Registers
Integer Multiply Unit and Registers
Loading and Storing: Addressing Modes
Data Types in Memory and Registers
Integer Data Types
Unaligned Loads and Stores
Floating-Point Data in Memory
Synthesized Instructions in Assembly Language
MIPS I to MIPS64 ISAs: 64-Bit (and Other) Extensions
To 64 Bits
Who Needs 64 Bits?
Regarding 64 Bits and No Mode Switch: Data in Registers
Basic Address Space
Addressing in Simple Systems
Kernel versus User Privilege Level
The Pull Picture: The 64-Bit View of the Memory Map
Pipeline Visibility
Coprocessor 0: MIPS Processor Control
CPU Control Instructions
Which Registers Are Relevant When?
CPU Control Registers and Their Encoding
Status Register (SR)
Cause Register
Exception Restart Address (EPC) Register
Bad Virtual Address (BadVAddr) Register
Count/Compare Registers: The On-CPU Timer
Processor ID (PRId) Register
Config Registers: CPU Resource Information and Configuration
EBase and IntCtl: Interrupt and Exception Setup
SRSCtl and SRSMap: Shadow Register Setup
Load-Linked Address (LLAddr) Register
CP0 Hazards-A Trap for the Unwary
Hazard Barrier Instructions
Instruction Hazards and User Hazards
Hazards between CP0 Instructions
How Caches Work on MIPS Processors
Caches and Cache Management
How Caches Work
Write-Through Caches in Early MIPS CPUs
Write-Back Caches in MIPS CPUs
Other Choices in Cache Design
Managing Caches
L2 and L3 Caches
Cache Configurations for MIPS CPUs
Programming MIPS32/64 Caches
The Cache Instruction
Cache Initialization and Tag/Data Registers
CacheErr, ERR, and ErrorEPC Registers: Memory/Cache Error Handling
Cache Sizing and Figuring Out Configuration
Initialization Routines
Invalidating or Writing Back a Region of Memory in the Cache
Cache Efficiency
Reorganizing Software to Influence Cache Efficiency
Cache Aliases
Exceptions, Interrupts, and Initialization
Precise Exceptions
Nonprecise Exceptions-The Multiplier in Historic MIPS CPUs
When Exceptions Happen
Exception Vectors: Where Exception Handling Starts
Exception Handling: Basics
Returning from an Exception
Nesting Exceptions
An Exception Routine
Interrupts
Interrupt Resources in MIPS CPUs
Implementing Interrupt Priority in Software
Atomicity and Atomic Changes to SR
Critical Regions with Interrupts Enabled: Semaphores the MIPS Way
Vectored and EIC Interrupts in MIPS32/64 CPUs
Shadow Registers
Starting Up
Probing and Recognizing Your CPU
Bootstrap Sequences
Starting Up an Application
Emulating Instructions
Low-level Memory Management and the TLB
The TLB/MMU Hardware and What It Does
TLB/MMU Registers Described
TLB Key Fields-EntryHi and PageMask
TLB Output Fields-EntryLoO-1
Selecting a TLB Entry-Index, Random, and Wired Registers
Page-Table Access Helpers-Context and XContext
TLB/MMU Control Instructions
Programming the TLB
How Refill Happens
Using ASIDs
The Random Register and Wired Entries
Hardware-Friendly Page Tables and Refill Mechanism
TLB Miss Handling
XTLB Miss Handler
Everyday Use of the MIPS TLB
Memory Management in a Simpler OS
Floating-Point Support
A Basic Description of Floating Point
The IEEE 754 Standard and Its Background
How IEEE Floating-Point Numbers Are Stored
IEEE Mantissa and Normalization
Reserved Exponent Values for Use with Strange Values
MIPS FP Data Formats
MIPS Implementation of IEEE 754
Need for FP Trap Handler and Emulator in All MIPS CPUs
Floating-Point Registers
Conventional Names and Uses of Floating-Point Registers
Floating-Point Exceptions/Interrupts
Floating-Point Control: The Control/Status Register
Floating-Point Implementation Register
Guide to FP Instructions
Load/Store
Move between Registers
Three-Operand Arithmetic Operations
Multiply-Add Operations
Unary (Sign-Changing) Operations
Conversion Operations
Conditional Branch and Test Instructions
Paired-Single Floating-Point Instructions and the MIPS-3D ASE
Exceptions on Paired-Single Instructions
Paired-Single Three-Operand Arithmetic, Multiply-Add, Sign-Changing, and Nonconditional Move Operations
Paired-Single Conversion Operations
Paired-Single Test and Conditional Move Instructions
MIPS-3D Instructions
Instruction Timing Requirements
Instruction Timing for Speed
Initialization and Enabling on Demand
Floating-Point Emulation
Complete Guide to the MIPS Instruction Set
A Simple Example
Assembly Instructions and What They Mean
U and Non-U Mnemonics
Divide Mnemonics
Inventory of Instructions
Floating-Point Instructions
Differences in MIPS32/64 Release 1
Regular Instructions Added in Release 2
Privileged Instructions Added in Release 2
Peculiar Instructions and Their Purposes
Load Left/Load Right: Unaligned Load and Store
Load-Linked/Store-Conditional
Conditional Move Instructions
Branch-Likely
Integer Multiply-Accumulate and Multiply-Add Instructions
Floating-Point Multiply-Add Instructions
Multiple FP Condition Bits
Prefetch
Sync: A Memory Barrier for Loads and Stores
Hazard Barrier Instructions
Synci: Cache Management for Instruction Writers
Read Hardware Register
Instruction Encodings
Fields in the Instruction Encoding Table
Notes on the Instruction Encoding Table
Encodings and Simple Implementation
Instructions by Functional Group
No-op
Register/Register Moves
Load Constant
Arithmetical/Logical
Integer Multiply, Divide, and Remainder
Integer Multiply-Accumulate
Loads and Stores
Jumps, Subroutine Calls, and Branches
Breakpoint and Trap
CP0 Functions
Floating Point
Limited User-Mode Access to "Under the Hood" Features
Reading MIPS Assembly Language
A Simple Example
Syntax Overview
Layout, Delimiters, and Identifiers
General Rules for Instructions
Computational Instructions: Three-, Two-, and One-Register
Immediates: Computational Instructions with Constants
Regarding 64-Bit and 32-Bit Instructions
Addressing Modes
Gp-Relative Addressing
Object File and Memory Layout
Practical Program Layout, Including Stack and Heap
Porting Software to the MIPS Architecture
Low-Level Software for MIPS Applications: A Checklist of Frequently Encountered Problems
Endianness: Words, Bytes, and Bit Order
Bits, Bytes, Words, and Integers
Software and Endianness
Hardware and Endianness
Bi-endian Software for a MIPS CPU
Portability and Endianness-Independent Code
Endianness and Foreign Data
Trouble with Visible Caches
Cache Management and DMA Data
Cache Management and Writing Instructions: Self-Modifying Code
Cache Management and Uncached or Write-Through Data
Cache Aliases and Page Coloring
Memory Access Ordering and Reordering
Ordering and Write Buffers
Implementing wbflush
Writing it in C
Wrapping Assembly Code with the GNU C Compiler
Memory-Mapped I/O Registers and "Volatile"
Miscellaneous Issues When Writing C for MIPS Applications
MIPS Software Standards (ABIs)
Data Representations and Alignment
Sizes of Basic Types
Sizes of "long" and Pointer Types
Alignment Requirements
Memory Layout of Basic Types and How It Changes with Endianness
Memory Layout of Structure and Array Types and Alignment
Bitfields in Structures
Unaligned Data from C
Argument Passing and Stack Conventions for MIPS ABIs
The Stack, Subroutine Linkage, and Parameter Passing
Stack Argument Structure in o32
Using Registers to Pass Arguments
Examples from the C Library
An Exotic Example: Passing Structures
Passing a Variable Number of Arguments
Returning a Value from a Function
Evolving Register-Use Standards: SGIs n32 and n64
Stack Layouts, Stack Frames, and Helping Debuggers
Variable Number of Arguments and stdargs
Debugging MIPS Designs-Debug and Profiling Features
The "EJTAG" On-chip Debug Unit
EJTAG History
How the Probe Controls the CPU
Debug Communications through JTAG
Debug Mode
Single-Stepping
The dseg Memory Decode Region
EJTAG CP0 Registers, Particularly Debug
The DCR (Debug Control) Memory-Mapped Register
EJTAG Breakpoint Hardware
Understanding Breakpoint Conditions
Imprecise Debug Breaks
PC Sampling with EJTAG
Using EJTAG without a Probe
Pre-EJTAG Debug Support-Break Instruction and CP0 Watchpoints
PDtrace
Performance Counters
GNU/Linux from Eight Miles High
Components
Layering in the Kernel
MIPS CPU in Exception Mode
MIPS CPU with Some or All Interrupts off
Interrupt Context
Executing the Kernel in Thread Context
How Hardware and Software Work Together
The Life and Times of an Interrupt
High-Performance Interrupt Handling and Linux
Threads, Critical Regions, and Atomicity
MIPS Architecture and Atomic Operations
Linux Spinlocks
What Happens on a System Call
How Addresses Get Translated in Linux/MIPS Systems
What's Memory Translation For?
Basic Process Layout and Protection
Mapping Process Addresses to Real Memory
Paged Mapping Preferred
What We Really Want
Origins of the MIPS Design
Keeping Track of Modified Pages (Simulating "Dirty" Bits)
How the Kernel Services a TLB Refill Exception
Care and Maintenance of the TLB
Memory Translation and 64-Bit Pointers
MIPS Specific Issues in the Linux Kernel
Explicit Cache Management
DMA Device Accesses
Writing Instructions for Later Execution
Cache/Memory Mapping Problems
Cache Aliases
CP0 Pipeline Hazards
Multiprocessor Systems and Coherent Caches
Demon Tweaks for a Critical Routine
Linux Application Code, PIC, and Libraries
How Link Units Get into a Program
Global Offset Table (GOT) Organization
MIPS Multithreading
What Is Multithreading?
Why Is MT Useful?
How to Do Multithreading for MIPS
MT in Action
Other Optional Extensions to the MIPS Instruction Set
MIPS16 and MIPS16e ASEs
Special Encodings and Instructions in the MIPS16 ASE
The MIPS16 ASE Evaluated
The MIPS DSP ASE
The MDMX ASE
MIPS Glossary
References
Books and Articles
Online Resources
Index

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