Fundamentals of Digital and Computer Design with VHDL

ISBN-10: 0073380695
ISBN-13: 9780073380698
Edition: 2012
List price: $157.99 Buy it from $24.21
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Description: This text book provides an introductory course in digital design and computer design. VHDL is used throughout the book to generate most of the designs in the book. No prerequisite is required for this book. The book is intended for students enrolled  More...

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Book details

List price: $157.99
Copyright year: 2012
Publisher: McGraw-Hill Education
Publication date: 10/1/2011
Binding: Hardcover
Pages: 736
Size: 8.25" wide x 10.25" long x 1.25" tall
Weight: 3.586
Language: English

This text book provides an introductory course in digital design and computer design. VHDL is used throughout the book to generate most of the designs in the book. No prerequisite is required for this book. The book is intended for students enrolled in electrical engineering , computer engineering, and computer science in their freshman or sophomore year. The first half of the book (Chapters 1 through 9) concentrates on digital design and the second half of the book (Chapters 10 through 19) concentrates on computer design and assembly language programming.

Preface
About the Authors
Boolean Algebra, Boolean Functions, VHDL, and Gates
Introduction
Basics of Boolean Algebra
Venn Diagrams
Black Boxes for Boolean Functions
Basic Logic Symbols
Boolean Algebra Postulates
Boolean Algebra Theorems
Proving Boolean Algebra Theorems
Deriving Boolean Functions from Truth Tables
Deriving Boolean Functions Using the 1s of the Functions
Deriving Boolean Functions Using the 0s of the Functions
Deriving Boolean Functions Using Minterms and Maxterms
Writing VHDL Designs for Simple Gate Functions
VHDL Design for a NOT Function
VHDL Design for an AND Function
VHDL Design for an OR Function
VHDL Design for an XOR Function
VHDL Design for a NAND Function
VHDL Design for a NOR Function
VHDL Design for an XNOR Function
VHDL Design for a BUFFER Function
VHDL Design for any Boolean Function Written in Canonical Form
More about Logic Gates
Equivalent Gate Symbols
Functionally Complete Gates
Equivalent Gate Circuits
Compact Description Names for Gates
International Logic Symbols for Gates
Number Conversions, Codes, and Function Minimization
Introduction
Digital Circuits versus Analog Circuits
Digitized Signal for the Human Heart
Discrete Signals versus Continuous Signals
Binary Number Conversions
Decimal, Binary, Octal, and Hexadecimal Numbers
Conversion Techniques
Binary Codes
Minimum Number of Bits for Keypads and Keyboards
Commonly Used Codes: BCD, ASCII, and Others
Modulo-2 Addition and Conversions between Binary and Reflective Gray Code
7-Segment Code
VHDL Design for a Letter Display System
Karnaugh Map Reduction Method
The Karnaugh Map Explorer
Using a 2-Variable K-Map
Using a 3-Variable K-Map
Using a 4-Variable K-Map
Don't-Care Outputs
Problems
Introduction to Logic Circuit Analysis and Design
Introduction
Integrated Circuit Devices
Analyzing and Designing Logic Circuits
Analyzing and Designing Relay Logic Circuits
Analyzing IC Logic Circuits
Designing IC Logic Circuits
Generating Detailed Schematics
Designing Circuits in NAND/NAND and NOR/NOR Form
Propagation Delay Time
Decoders
Designing Logic Circuits with Decoders and Single Gates
Multiplexers
Designing Logic Circuits with MUXs
Hazards
Function Hazards
Logic Hazards
Problems
Combinational Logic Circuit Design with VHDL
Introduction
VHDL
The Library Part
The Entity Declaration
The Architecture Declaration
Comments about a Dataflow Design Style
Comments about a Behavioral Design Style
Comments about a Structural Design Style
Dataflow Design Style
Behavioral Design Style
Structural Design Style
Implementing with Wires and Buses
VHDL Examples
Design with Scalar Inputs and Outputs
Design with Vector Inputs and Outputs
Common VHDL Constructs
Problems
Bistable Memory Device Design with VHDL
Introduction
Analyzing an S-R NOR Latch
Simple On/Off Light Switch
Circuit Delay Model for an S-R NOR Latch
Characteristic Table for an S-R NOR Latch
Characteristic Equation for an S-R NOR Latch
PS/NS Table for an S-R NOR Latch
Timing Diagram for an S-R NOR Latch
Analyzing an S-R NAND Latch
Circuit Delay Model for an S-R NAND Latch
Characteristic Table for an S-R NAND Latch
Characteristic Equation for an S-R NAND Latch
PS/NS Table for an S-R NAND Latch
Timing Diagram for an S-R NAND Latch
Designing a Simple Clock
Designing a D Latch
Gated S-R Latch Circuit Design
D Latch Circuit Design with S-R Latches
D Latch Circuit Design via the Characteristic Table for a D Latch
Timing Diagram for a D Latch
Creating a Clock via a D Latch
Creating an 8-bit D Latch
Designing D Flip-Flop Circuits
Designing Master-Slave D Flip-Flop Circuits
Designing D Flip-Flop Circuits with S-R NAND Latches
Timing Diagram for Positive Edge-Triggered D Flip-Flop
Problems
Simple Finite State Machine Design with VHDL
Introduction
Synchronous Circuits
Creating D-type Flip-Flops in VHDL
Designing Simple Synchronous Circuits
Counter Design Using the Algorithmic Equation Method
Nonconventional Counter Design Using the Algorithmic Equation Method
Counter Design Using the Arithmetic Method
Frequency Division (Slowing Down a Fast Clock Frequency)
Counter Design Using the PS/NS Tabular Method
Nonconventional Counter Design Using the PS/NS Tabular Method 177 Problems
Computer Circuits
Introduction
Three-State Outputs and the Disconnected State
Data Bus Sharing for a Microcomputer System
More about XOR and XNOR Symbols and Functions
Odd and Even Functions
Single-Bit Error Detection System
Comparators and Greater Than Circuits
Adder Design
Designing a Half Adder Module
Designing a Full Adder Module
Designing and Using Ripple-Carry Adders and Subtracters
Propagation Delay Time for Ripple-Carry Adders
Designing Carry Look-Ahead Adders
Propagation Delay Time for Carry Look-Ahead Adders
Problems
Circuit Implementation Techniques
Introduction
Programmable Logic Devices
PROMs and LUTs
PLAs
PALs or GALs
Designing with PROMs or LUTs
Designing with PLAs
Designing with PALs or GALs
Positive Logic Convention and Direct Polarity Indication
Signal Names
Analyzing Equivalent Circuits for the PLC and the DPI Systems
More about MUXs and DMUXs
Designing MUX Trees
Designing DMUX Trees
Problems
Complex Finite State Machine Design with VHDL
Introduction
Designing with the Two-Process PS/NS Method
Explanation of CPLDs and FPGAs and State Machine Encoding Styles
Summary of Finite State Machine Models
Designing Compact Encoded State Machines with Moore Outputs
Designing One-Hot Encoded State Machines with Moore Outputs
Designing Compact Encoded State Machines with Moore and Mealy Outputs
Designing One-Hot Encoded State Machines with Moore and Mealy Outputs
Using the Algorithmic Equation Method to Design Complex State Machines
Improving the Reliability of Complex State Machine Designs
Additional State Machine Design Methods
Two-Assignment PS/NS Method
Hybrid PS/NS Method
Problems
Basic Computer Architectures
Introduction
Generic Data-Processing System or Computer
Harvard-Type Computer and RISC Architecture
Princeton (von Neumann)-Type Computer and CISC Architecture
Overview of VBC1 (Very Basic Computer 1)
Design Philosophy of VBC1
Programmer's Register Model for VBC1
Instruction Set Architecture for VBC1
Format for Writing Assembly Language Programs
Problems
Assembly Language Programming for VBC1
Introduction
Instruction Set for VBC1
The IN Instruction
The OUT Instruction
The MOV Instruction
The LOADI Instruction
The ADDI Instruction
The ADD Instruction
The SR0 Instruction
The JNZ Instruction
Programming Examples and Techniques for VBC1
Unconditional Jump
Labels
Loop Counter
Program Runs Amuck
Subtraction Instruction
Multiply Instruction
Divide Instruction
Problems
Designing input/Output Circuits
Introduction
Designing Steering Circuits
Designing Bus Steering Circuits
Designing Loadable Register Circuits
Designing Input Circuits
Designing an Input Circuit Driven by Four Slide Switches
Designing Output Circuits
Designing an Output Circuit to Drive Four LEDs
Designing an Output Circuit to Drive a 7-Segment Display
A Closer Look at the Circuitry for Display 0
Combining Input and Output Circuits to Form a Simple I/O System
Alternate VHDDL Design Styles
Problems
Designing Instruction Memory, Loading Program Counter, and Debounced Circuit
Introduction
Designing an Instruction Memory
Coding Alterations for Instruction Memory
Initializing Instruction Memory for VBC1 at Startup
Designing a Loading Program Counter
Designing a Debounced One-Pulse Circuit
Design Verification for a Debounced One-Pulse Circuit
Problems
Designing Multiplexed Display Systems
Introduction
Multiplexed Display System for Four 7-Segment LED Displays
Designing a Multiplexed Display System Using VHDL
Designing Module l: A 4-to-l MUX Array
Designing Module 2: A HEX Display Decoder
Designing Module 3: A 2-bit Counter and a Frequency Divider
Designing Module 4: A 2-to-4 Decoder
Complete Design of a Multiplexed Display System Using a Flat Design Approach
Complete Design of a Multiplexed Display System Using a Hierarchal Design Approach
Designing a Word Display System Using a Flat Design Approach
Problems
Designing Instruction Decoders
Introduction
Purpose of the Instruction Decoder
Instruction Decoder Truth Tables for the EM, OUT, and MOV Instructions
Designing an Instruction Decoder for the IN Instruction
Designing an Instruction Decoder for the OUT and MOV Instructions
Instruction Decoder Truth Table for the LOADI Instruction
Instruction Decoder Truth Table for the ADDI Instruction
Instruction Decoder Truth Table for the ADD Instruction
Instruction Decoder Truth Table for the SR0 Instruction
Designing an Instruction Decoder for the SR0 Instruction
Instruction Decoder Truth Table for the JNZ Instruction
Designing an Instruction Decoder for the JNZ Instruction
Designing an Instruction Decoder for VBC1
Problems
Designing Arithmetic Logic Units
Introduction
Utilization of the Arithmetic Logic Unit
Designing the LOADI Instruction Part of the ALU
Designing the ADDI Instruction Part of the ALU
Designing the ADD Instruction Part of the ALU
Designing the SR0 Instruction Part of the ALU
Designing an ALU for VBC1
Additional Circuit Designs with VHDL
Designing Additional ALU Circuits
Designing Shifter Circuits
Designing Barrel Shifter Circuits
Designing Shift Register Circuits
Problems
Completing the Design for VBC1
Introduction
Designing a Running Program Counter
Combining a Loading and a Running Program Counter
Designing a Run Frequency Circuit and a Speed Circuit
Designing Circuits to Provide a Loader for Instruction Memory for VBC1
Problems
Assembly Language Programming for VBC1-E
Introduction
Instruction Summary
Input, Output, and Interrupt Instructions
Data Memory Instructions
Arithmetic and Logic Instructions
Shift and Rotate Instructions
Jump, Jump Relative, and Halt Instructions
More about Interrupts and Assembler Directives
Complete Instruction Set Summary for VBC1-E
Problems
Designing Input/Output Circuits for VBC1-E
Introduction
Designing the Input Circuit for VBC1-E
Instruction Decoder Truth Table for the Modified IN Instruction for VBC1-E
Designing the Output Circuit for VBC1-E
Instruction Decoder Truth Table for the Modified OUT Instruction for VBC1-E
Designing an Instruction Decoder for the Modified IN and OUT Instructions for VBC1-E
Designing an Instruction Decoder for the LOADI, ADDI, and JNZ Instructions for VBC1-E
Problems
Designing the Data Memory Circuit for VBC1-E
Introduction
Designing the Data Memory for VBC1-E
Designing Circuits to Select the Registers and Data for VBC1-E
Instruction Decoder Truth Tables for the STORE and FETCH Instructions for VBC1-E
Designing an Instruction Decoder for the STORE and FETCH Instructions for VBC1-E
Designing an Instruction Decoder for the MOV Instruction for VBC1-E
Problems
Designing the Arithmetic, Logic, Shift, Rotate, and Unconditional Jump Circuits for VBC1-E
Introduction
Designing the Arithmetic and Logic Instructions Part of the ALU for VBCl-E
Designing the Instruction Decoder for the Arithmetic and Logic Instructions for VBC1-E
Designing the Shift and Rotate Instructions Part of the ALU for VBCl-E
Designing the Instruction Decoder for the Shift and Rotate Instructions for VBC1-E
Designing the JMP and JMPR Circuits for VBC1-E
Designing the Instruction Decoder for the JMP and JMPR Instructions for VBC1-E
Problems
Designing a Circuit to Prevent Program Execution During Manual Loading for VBC1-E
Introduction
Designing a Circuit to Modify Manual Loading for VBC1-E
Modifying the Instruction Decoder for Manual Loading for VBC1-E 495 Problems
Designing Extended Instruction Memory for VBC1-E
Introduction
Modifying the Instruction Memory to Add Extended Instruction Memory for VBC1-E
Modifying the Running Program Counter Circuit for VBC1-E
Modifying the Proper Address Circuit for VBC1-E
Modifying the Loading Program Counter Circuit for VBC1-E
Modifying the JMPR Circuit for VBC1-E
Problems
Designing the Software interrupt Circuits for VBC1-E
Introduction
Designing the Modified Circuit for the Running Program Counter and the Select Circuit for VBC1-E
Designing the Circuit to Store PCPLUS1 for VBC1-E
Instruction Decoder Truth Tables for the INT and IRET Instructions for VBC1-E
Designing the Instruction Decoder for the INT and BRET Instructions for VBC1-E
Problems
Completing the Design for VBC1-E
Introduction
Designing a Debounced One-Pulse Trigger Interrupt Circuit and Modifying the RPC Circuit for VBC1-E
Designing Circuits for Displaying the Signal RETA for VBC1-E
Designing Circuits to Provide a Loader for Instruction Memory for VBC1-E
Problems
Appendices
Laboratory Experiments
Designing and Simulating Gates
Completing the Design Cycle
Designing and Testing a Keypad Encoder System
Designing and Testing a Check Gates System
Designing and Testing a Custom Decimal Display Decoder System
Designing and Testing a D Latch and a D Flip-Flop with a CLR Input
Designing and Testing an 8-bit Register and a D Flip-Flop with a PRE Input
Designing and Testing a Simple Counter System-A One-Hot Up Counter with 8 Bits
Designing and Testing a Simple Counter System-A Gray Code Counter with 2 Bits
Designing and Testing a Simple Nonconventional Counter System-A Robot Eye Circuit
Designing and Testing a Simple Nonconventional Counter-A Smiley Face Circuit
Designing and Testing a Simple Error Detection System Using a Flat Design Approach
Designing and Testing a 4-bit Simple Adder-Subtractor System Using a Hierarchal Design Approach
Designing and Testing a LUT Design System Using a Flat Design Approach
Designing and Testing a One-Hot Up/Down Counter System Using a Flat Design Approach
Designing and Testing a 10-State Counter System Using a Hierarchal Design Approach
Working with EASY1 (Editor/Assembler/Simulator) for VBC1
Writing and Simulating Programs for VBCl with EASY1
Designing and Testing VBC1 (Data Path Unit)
Designing and Testing VBC1 (Instruction Memory Unit)
Designing and Testing VBC1 (Monitor System)
Designing and Testing VBC1 (Instruction Decoder)
Designing and Testing VBC1 (Arithmetic Logic Unit)
Designing and Testing VBC1 (Final Hardware Design for VBC1)
Designing a Loader for Instruction Memory for VBC1
Writing Assembly Language Programs and Running Them on VBC1
Designing and Testing VBC1-E (IN, OUT, and Unchanged Instructions)
Designing and Testing VBC1-E (MOV and Data Memory Instructions)
Designing and Testing VBC1-E (Almost All Instructions)
Designing and Testing VBC1-E (Modified Manual Loading)
Designing and Testing VBC1-E (Add Extended Instruction Memory)
Designing and Testing VBC1-E (INT and DIET Instructions)
Designing and Testing VBC1-E (Final Hardware Design for VBC1-E)
Designing a Loader for Instruction Memory for VBC1-E
Obtaining Simulations via the VHDL Test Bench Program
Introduction
Example 1-Combinational Logic Design (project: AND_3)
Example 2-Synchronous Sequential Logic Design (project: DFF)
FPGA Pin Connections-Handy Reference
BASYS 2 Board
NEXYS 2 Board
Memory Loader I/O Pin Connections for the FPGAs on the BASYS 2 and NEXYS 2 Board
FX2 MIB (Module Interface Board)-Add-on Board for NEXYS 2
D EASY1 Tutorial
Introduction
EASY1 Screen or GUI
EASY1 Layout
How to Use EASYl
Example 1-A Simple Input/Output Program
Example 2-Input/Output Program Modified to Run Continuously
Example 3-A Simple State Machine Program
Example 4-A Complex State Machine Program
Example 5-Generating Time Delays
Using EASY1 to Generate Machine Code for VBC1
Three Methods for Loading Instructions into Memory
Loading Memory Manually
Initializing Memory at Startup
Loading Memory via the Memory Loader Program
Index

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